[SV]Verilog系统任务及应用实例 ---- 显示任务及应用案例（Timing check tasks and example）

                          Verilog系统任务及应用实例

                                         ---- 显示任务及应用案例（display tasks and example）

一、显示任务

 1.1、显示任务列表

No.	Task	Description
1	$display([ mcd, ] "text", signal, signal, ...);	$display and $write prints the text when the statement is executed during simulation. The only difference between the two is that $display writes out a newline character at the end of the text, whereas $write does not.
2	$write( [ mcd, ] "text", signal, signal, ...);	功能同$display()，只是行尾不会添加换行符"\n"
3	$strobe( [ mcd, ] "text", signal, signal, ...);	prints the text when all simulation events in the current time step have executed. A newline is automatically added to the text.
4	$monitor( [ mcd, ] "text", signal, signal, ...);	prints the text whenever one of the signals in the signal list changes. A newline is automatically added to the text.

• mcd = expression       // multi-channel descriptor

 1.2、 格式控制符列表

No.	格式控制符	作用描述
1	%b or %B	Binary format，%0b表示字段总是足够大，可以显示值
2	%d or %D	Decimal format (default)
3	%h or %H	Hexadecimal format
4	%o or %O	Octal format
5	%e or %E	Real in exponential format（指數形式表示的實數）
6	%f or %F	Real in decimal format(十進制實數)
7	%g or %G	Real in decimal or exponential format (shortest result)
8	%c or %C	Character
9	%s or %S	String
10	%t or %T	Time format
11	%m or %M	Hierarchical name
12	%v or %V	Net signal strength

• After the % character a minimum field width value may be include (e.g. %6d).
• A minimum field width of zero means that the field will always be just big enough to display the value.
• The %e and %f may specify the field width for both sides of the decimal point (e.g. %6.2f).

 1.3、转义字符列表

No.	转义字符	含义
1	\n	Newline
2	\t	Tab
3	\\	Backslash
4	\ddd	Octal code 扫描二维码关注公众号，回复： 11168003 查看本文章
5	%%	Percent sign

• If the signal list contains two adjacent commas, a space is written out at that point.

 1.4、应用案例

bit A  = 1;

$display("The binary value of A is: %b", A);

$write("The register values are: ", Reg1, Reg2, Reg3, "\n");


module display_test()

  initial begin
    A = 0;
    $display(A);      // displays 0
    $strobe(A);       // displays 1
    A = 1;
  end

endmodule

二、參考資料

 2.1、Link

 2.2、Link