#The flower of the cliff, the more fragrant the more free
Every time there is a problem with Robei EDA, I wonder whether it is my brain stupid or EDA brain disability; but every time I solve this problem, I feel that I am stupid to have this problem. Wonderful ah ~
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after robei EDA was added .v files, integrated system, robei The automatically generated code does not include the include format that we usually use in Verilog code.
·include''sdram_para.v''
The code automatically generated by robei does not have this statement. If you directly use the .v file generated by robei to synthesize it on quartus, an error will occur, telling you that the included file is missing. (This is very dogged)
Later, I asked the engineer, and was told by the engineer that the code file generated directly will not automatically generate the include code. Robei included this code in another way.
When Robei synthesizes fpgafiles.vfthe files, a file called is generated . This includefile includes all files, including sdram_para for "define". According to Robei engineers, it is only necessary to import this file to perform synthesis. BUT! A classmate from Guanghua and I both found that there was a problem in synthesis, and it was quite troublesome.
The problem is:
1. Only import the fpgafiles file for compilation, Quartus will report an error saying that the top file cannot be found.
2. If you import all the Verilog code generated by Robei and this fpgafiles into the project, Quartus will report an error saying that this sdram_para.vfile cannot be found , and a total of 44 errors will be generated.