I copied an FPGA project, and found the following error report when running:
Error (262006): File "stp1.stp" is not a valid Signal Tap File - ignoring
checked it, there is no stp1.stp file, it is estimated that it is deleted. However, the compilation link was not deleted in the project settings, so it could not be found when linking, and an error was reported.
The best way is to create a signal tap file yourself, choose any name you want, and associate it with the project. The project will automatically replace the original non-existent name, OK.
However, SIGNALTAP occupies resources after all. What if you just want to delete this trouble? Tried each setting option, it seems that this trouble cannot be completely eliminated in the setting (strange???),
I had to use the stupid method to open the project file *.qsf file, find the place where the stp1.stp file name is, and delete it directly.
set_global_assignment -name ENABLE_SIGNALTAP OFF <------------------Delete this line: The author has obviously closed SIGNAL TAP; but stp1.stp has not been cleaned up.
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp <------------------ delete this line,
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
OK, the problem is solved and no more errors are reported. But a new problem is coming, it will appear when running MODELSIM,
Error (138003): Can't write incremental compilation assignments. Quartus Prime Settings File xxx.qsf is unwritable.
The solution is to close modelsim and re-run tools->Run Simulation Tool->Rtl Simulation.
I have to sigh, it's not a solution, it's just that there is no problem for the time being.