Do you know the relationship between LPDDR and DDR?

What is LPDDR?

Not much to say, let’s go to the vernacular first, a netizen summed it up very well: Simply put, DRR4 is a standard voltage version of PC and server memory, LPDDR4 is a low-voltage and low-power memory used by embedded mobile devices such as mobile phones, and LPDDR4X is It is an upgraded version of LPDDR4, and the power consumption is reduced under the same performance!

LP===Low Power

Take a look at my brother's blog in detail below.

LPDDR4 is the mobile equivalent of DDR4 memory. Compared to DDR4, it has lower power consumption, but at the cost of bandwidth . LPDDR4 has two 16-bit channels, resulting in a total bus length of 32 bits per DIMM. In comparison, DDR4 has 64-bit channels per DIMM.

At the same time, however, LPDDR4 has a wider prefetch width of 16n, for a total of (16 words x 16 bits) 256 bits/32 bytes per lane, twice the sum of the two lanes.

DDR4, on the other hand, has two 8n prefetch banks per channel. The two memory banks are separate and two independent 8n prefetches can be performed. This is done by time multiplexing its internal repository using a multiplexer. Each group has a total of 8 words x 64 bits = 512 bits (64 bytes) per cycle.

LPDDR4 reduces power consumption compared to DDR4, but does so at the expense of bandwidth. LPDDR4 has two 16-bit channels, resulting in a total 32-bit bus. In comparison, DDR4 has 64-bit channels.

LPDDR4 also has more flexible burst lengths ranging from 16 to 32 (256 or 512 bits, 32 or 64 bytes), although 16 BLs are used in most cases. DDR4, on the other hand, is limited to 8 burst lengths (128 bits or 16 bytes) per cycle, although each bank can perform additional transfers (from two different bank groups).

To understand what the burst length means, you need to know how the memory is accessed.

When the CPU or cache requests new data, the address is sent to the memory module and the required row, then the column is found (if not present, the new row is loaded). Keep in mind that there will be a delay with every operation. Afterwards, the entire column is sent over the memory bus in bursts. For DDR4, each burst is 8 (or 16B). With DDR5 this has increased to as many as 32 (64B max). There are two bursts per clock, which occur at the effective data rate. Also, similar to LPDDR4, DDR5 has two 32-bit channels per DIMM, for a total of four channels in a dual-DIMM configuration. Prefetch and BL have also been increased to 16. This number is ideal because every cache line in memory is the same size.

The design makes LPDDR4 more power efficient than standard DDR4 memory, ideal for use in smartphones with up to 8-10 hours of battery standby time. Micron's LPDDR4 RAM topped the mark with a clock of 2133 MHz and a transfer rate of 4266 MT/s, while Samsung was a close second with a clock of 1600MHz and a transfer rate of 3200 MT/s. Also, as you can see in the table below (from Wikipedia), LPDDR4 (1.1v) has a much lower voltage than DDR4 (1.3v), although it has a similar or higher I/O bus clock.

Low Power DDR

Lastly, there is the issue of memory banks. LPDDR4 is once again optimized for low-power performance, while DDR4 memory is the opposite. DDR4 memory consists of groups of 16 banks, each packing four separate banks, while LPDDR4 and LPDD4X DIMMs have a total of eight banks per channel, so the total is 16 (16 bits x 2). LPDDR5 uses a structure similar to DDR4, but that's another discussion.

LPDDR4 vs. LPDDR4X: What's the Difference?

Similar to how DDR5 reduces voltage and power consumption, LPDDR4X does the same. It reduces the I/O voltage by 50% (1.12 to 0.61v), which greatly reduces the power consumption of the memory as well as the memory controller.

In addition, the speed has also been increased from 3200MT/s to 4266MT/s (without OC). This is a result of the faster I/O bus clock (1600MHz to 2134MHz) and memory array (200-266.7MHz). The command and address buses have reserved 6-bit SDR space. Finally, it takes up less on-chip space and can contain up to 12GB of DRAM in a single package. On the downside, LPDDR4X is not backward compatible with LPDDR4. Even if a device is compatible with faster LPDDR4 memory, it may not work with LPDDR4X.

DDR literacy - noun analysis in DDR

• AS: Row Address Strobe, row address strobe;

• CAS: Column Address Strobe, column address strobe;

• tRCD: RAS to CAS Delay, RAS to CAS delay;

• CL: CAS Latency, CAS latency (also known as read latency), the time period from CAS and read commands to the first data output;

• RL: Read Latency, read latency;

• tAC: Access Time from CLK, the access time after the clock is triggered, from the rising edge of a clock before the data output on the data I/O bus to the time when the data is transmitted to the I/O bus;

• tWR: Write Recovery Time, write back, to ensure reliable writing of data and leave enough writing/correction time, is used to indicate the amount of time between the last valid operation of the same bank and the precharge command;

• BL: Burst Lengths, burst length, burst refers to the way of continuous data transmission between adjacent storage units in the same row, the number of storage units (columns) involved in continuous transmission is the burst length (SDRAM), in DDR SDRAM refers to the number of cycles of continuous transmission;

• Precharge: L-Bank closes the existing working line and prepares to open a new line;

• tRP: Precharge command period, the precharge effective period, after sending the precharge command, it will take a period of time to allow the RAS line valid command to be sent to open a new working line;

• AL: Additive Latency, additional latency (DDR2);

• WL: Write Latency, the latency period from the write command to the first data input;

• tRAS: Active to Precharge Command, line valid to precharge command interval period;

• tDQSS: WRITE Command to the first corresponding rising edge of DQS, the delay time of DQS relative to the write command;

Logic Bank

The inside of SDRAM is a storage array. If you want to accurately find the required storage unit, you must first specify a (row), and then specify a column (Column). This is the basic principle of memory chip addressing.

Chip width

The amount of data at one transfer rate of an SDRAM memory chip is the bit width of the chip, so the capacity of this storage unit is the bit width of the chip (also the bit width of the L-Bank);

The number of storage units = the number of rows * the number of columns (to obtain the number of storage units in an L-Bank) The number of L-Banks can also be used to represent the capacity of the chip in the form of M W, M is the total number of storage units in the chip, and the unit is megabytes ( English abbreviation M, the exact value is 1048576), W represents the capacity of each storage unit, which is the bit width of the SDRAM chip, and the unit is bit;

• The internal storage unit capacity of DDR SDRAM is twice the chip bit width (chip I/O port bit width);

• The internal storage unit capacity of DDR2 SDRAM is four times the bit width of the chip;

• The internal storage unit capacity of DDR3 SDRAM is eight times the bit width of the chip;

• The internal storage unit capacity of DDR4 SDRAM is eight times the bit width of the chip.

参考资料：
https://mp.weixin.qq.com/s?__biz=MzA4NjQwNjMwOA==&mid=2650482661&idx=3&sn=78ffd8d0c704c5da4060eec9eb7fbc1d&chksm=87c6a22eb0b12b38514069f0ceff622cd20bd92c12d72ad5c049e8d0853b52f56d1529d1ffce&scene=27

https://baijiahao.baidu.com/s?id=1700533276647105969&wfr=spider&for=pc