FPGA development process in detail is the use of EDA tools for FPGA chip process development.
FPGA development process as shown in detail, including the circuit design, the design input, synthesis (optimization), layout (implementation and optimization), arranged five programming steps, wherein there are functional simulation, the static simulation, simulation timing simulation three and synthesis constraints, layout constraints (including location constraints and timing constraints) the two major constraints, and so on.
1, the circuit design (FPGA Design)
Before circuit design, the first to be carried out is the design and verification algorithms (done in Python or in Matalb) (As to how the algorithm is generally based on market demand to develop, and this is not in this discussion) , program feasibility studies, architectural design and FPGA chip selection and other preparatory work. The system engineer to the tasks, such as metrics and complexity, functionality and stability of the system, the work speed (operating frequency and delay) and the chip itself resources, cost, power consumption, etc., trade-offs, a reasonable choice design (the fixed-point design optimization) and a suitable type of device (e.g., ships or Zynq Artix or Zynq UltraScale +, etc. ).
Circuit design method is divided into top-down and bottom-up design method. Generally using top-down design method (starting from the system design, to gradually modular design, device design and layout design to promote more physical level): Starting from the start the system design, then the overall system is divided into a plurality of basic units, and then divide each basic unit is the next level of the base unit, has been to do so until you can directly use the EDA libraries so far. Finally, he began Coding.
2, the input design (Design Entry)
It refers to the design of the input circuit designer involved in the development of certain software requirements expressed in the form, and input to the corresponding software processes. The most common expression of design input for the IP core, schematics (Schematic) and HDL text input.
Here IP can be divided into three categories according to sources, the first from the previous design is created inside the module (Design by Yourself), a second FPGA manufacturers, the third is from IP vendors.
FPGA manufacturers and IP vendors can provide us with a different IP at different times FPGA development. Let us know that they are not encrypted RTL-level IP, encrypted RTL-level IP, without layout netlist-level IP, post-layout netlist IP.
3, integrated (Synthesis)
Comprehensive generally refers to high-level abstraction level of design description automatically translate into a lower-level description of the process. And integrated in the FPGA software tool means is automatically converted as follows, or, the synthesizer is capable of schematics or HDL language text, the circuit is described to be by a compiler or array, RAM, flip-flops, registers, etc. Logic tool unit consisting of a circuit configuration of the netlist.
Comprehensive including compilation, mapping and optimization (also can be separated not be integrated included), the compiler is HDL → gate-level netlist, the mapping is the gate-level netlist → LUT, the optimization is to optimize the design (It should be noted that in the development process of Altera , the compilation, mapping process described collectively in accordance with our integrated, and in the development process of Xilinx, get input from the gate-level netlist design process is called synthesis, and the mapping process comes down to it is called a sub-step implementation in. but this is a small problem, the overall process was followed in this order).
Integrated form:
1, the algorithm converts the RTL level description of the behavior (Register Transfer Level) (register transfer level), which describes the behavior of the structure to be described.
2, converts the RTL level description of the logic gate stage (including triggers), referred to as logic synthesis.
3, the logic gate representations to represent the layout or configuration of PLD netlist representation; ASIC can be produced according to the layout information, with the netlist configuration can be done based on the system implemented in the PLD.
Software program compiler to compile a program written in C language or assembly code that stream is 0, and the hardware is a comprehensive program written in languages like Verilog HDL into specific netlist structure.
In circuit design netlist (the Netlist) is a connection relationship between each circuit element described, is generally a relatively simple follow a tagged text file syntax. (Baidu Encyclopedia gate-level netlist). RTL-level design synthesis logic synthesis is according to the constraints described in Verilog HDL or VHDL, may be converted to the basic structure of a gate array FPGA / CPLD is mapped netlist file.
4, layout (Place & Route)
Before talking about layout, we must first talk about realization (Implementation). Configuration is achieved integrated logic netlist to generate specific FPGA chip, and the layout is one of the most important process. Vivado implemented as shown in particular, into the design to initialize (Design Initialization), optimized design (Opt Design), power-optimized design (Power Opt Design), layout design (Place Design), the power optimization design layout (Post -Place Power Opt design), the optimized design of the physical layout (post-Place Phys Opt design) , layout design (Route design), the optimized design of the physical cabling (post-Route Phys Opt design) , generates a bit stream (Write bitstream).
It refers to the layout mapping logic integrated circuit netlist generated to achieve a particular target device, and may be generated during a final download files.
The layout is divided into small blocks of the logical position of the device the specific internal logic resources, and make them easy to connect;
The wiring is the use of routing resources to complete the connection between the devices between the function modules and the feedback signal.
It will produce the following number of important documents after the completion of layout:
1, the chip resource consumption report.
2, EDA tools for other output file, such as EDIF files.
3、产生延时网表结构，以便于进行精确的时序仿真，这时候的仿真结果能够比较精确地预测未来芯片的实际性能。如果仿真结果达不到设计要求，就需要修改源代码或者选择不同速度的器件，直至满足设计要求，例如普通加法器改为超前进位加法器，普通乘法器改为 Booth 乘法器等等，通过减少关键路径来满足时序要求。
4、器件编程文件：如用于 FPGA 配置的 SOF，JAM，BIT 等格式的文件，用于 CPLD 编程的 JEDEC，POF 等格式的文件。由于布局布线与芯片的物理结构直接相关，所以一般选择芯片制造商提供的开发工具进行此项工作。
约束（Constraint）（附加）：
约束分为综合约束和布局布线约束，布局布线约束又可以分为位置约束、时序约束。约束，就是对这些操作环节定制规则，定制条件，比如引脚约束和时序约束。一般开发环境会对这些约束有个默认，这些默认的设置对大部分情况下还是适用的，但是通常布局布线约束中的 I/O 约束是我们每一个工程都必须给定的。
仿真（Simulation）（附加）：
仿真指的是对所设计电路功能的验证。仿真包括（功能）RTL 仿真、（门级）静态仿真和时序仿真。
RTL 仿真就是对你的 HDL 代码仿真，对你的 RTL 级描述的设计进行测试。RTL 仿真，又叫功能仿真，也称为前仿真，是在编译之前对用户所设计的电路进行逻辑功能验证，此时的仿真没有任何延迟信息，是处于理想化状态的，仅对初步的功能进行验证。
静态仿真指对综合之后的 LUT 门级网表。静态仿真，又叫门级仿真，也称为综合后仿真，在仿真时，把综合生成的标准延时文件反标注到综合仿真模型中去，可估计门延时带来的影响，但不能估计线延时，此时的仿真也并不是十分准确，和布局布线后的实际情况还是有一定差距的。
时序仿真在选择具体器件并完成布局布线后进行的包含延时的仿真。时序仿真，又叫布局布线后仿真，是指将布局布线的延时信息反标注到设计网表中来检测有无时序违规的现象（即是否满足时序约束条件或器件固有的时序规则，如建立时间、保持时间等等。而此时，不同器件的内部延时都不太一样，不同的布局、布线方案所生成的延时也不太一样）。时序仿真包含的延迟信息最全，也最精确，能较好地反映芯片的实际工作情况。
5、编程配置（Program & Configuration）
编程配置就是生成比特流之后将比特流载入 FPGA 芯片中的一个过程。
把布局布线后生成的编程文件装入 PLD 器件中的过程称为下载。
通常将对基于 EEPROM 工艺的非易失结构 CPLD 器件的下载称为编程。一般芯片编程是指产生使用的数据文件（如比特流文件（.bit）），然后将编程数据下载到 FPGA 芯片中。
而将基于 SRAM 工艺结构的 FPGA 器件的下载称为配置。