SystemVerilog Parameters
There are two ways to define constants:
- parameter
- `define
一、Parameter
Parameters must be defined within module boundaries using the keyword parameter.
A parameter is a constant that is local to a module that can optionally be redefined on an instance. Parameters are typically used to specify the width of variables and time delays.
1、Parameter example
module mem_model #(
parameter ADDR_WIDTH=8;
parameter DATA_WIDTH=32;)
(clk, addr, data);
input clk;
input [ADDR_WIDTH-1:0] addr;
output [DATA_WIDTH-1:0] data;
.....
.....
endmodule
2、Parameter redefinition
Parameter values are not allowed to modify at runtime but can be modified using the defparam statement and #delay specification with module instantiation.
//Creates mem_1 instance with default addr and data widths.
mem_model mem_1 (.clk(clk),
.addr(addr_1),
.data(data_1));
//Creates mem_2 instance with addr width = 4 and data width = 8.
mem_model #(4,8) mem_2 (.clk(clk),
.addr(addr_2),
.data(data_2));
//Creates mem_3 instance with addr width = 32 and data width = 64.
mem_model #(32,64) mem_3 (.clk(clk),
.addr(addr_3),
.data(data_3));
//Creates mem_4 instance with default addr width and data width = 64.
mem_model #(DATA_WIDTH=64) mem_4 (.clk(clk),
.addr(addr_3),
.data(data_3));
//ADDR_WIDTH value of mem_1 instance can be changed by using defparam as shown below,
defparam hierarchical_path.mem_1.ADDR_WIDTH = 32;
二、`define Macro
The `define compiler directive is used to perform global macro substitution and remain active for all files read/compiled after the macro definition.
It will available until another macro definition changes the value or until the macro is undefined using the `undef compiler directive.
`define WIDTH 8
to avoid redefincation `ifdef can be used,
`ifdef WIDTH
// do nothing (better to use `ifndef)
`else
`define WIDTH 8
`endif
`ifndef WIDTH
`define WIDTH 8
`endif
`ifdef can be used as if..else
`ifdef TYPE_1
`define WIDTH 8
`else
`define WIDTH 32
`endif
//`ifdef can also be used to avoid redefining/recompiling the module/class,
//In the below example,
//definition of MODULE_1 is checked, if it is not defined then MODULE_1 will be defined and compiles the module/class inside the `ifndef - `endif.
//suppose if the same file is compiled twice then at the first time MODULE_1 will get defined, so second time `ifndef condition will not be satisfied.
`ifndef MODULE_1
`define MODULE_1
module mem;
....
....
endmodule
`endif