求问这个分频模块被调用后为什么就没用了呢（仿真无结果）
//被测信号产生模块
module Test_Signal(clk_50MHz,clk_10MHz);
input clk_50MHz;
output clk_10MHz;
div_5 U1(
.clkin(clk_50MHz),
.clkout(clk_10MHZ)
);
endmodule
//五分频
module div_5(clkin,clkout);
input clkin;
output clkout;
reg [2:0] step1, step2;
always @(posedge clkin )
begin
case (step1)
3’b000: step1<=3’b001;
3’b001: step1<=3’b011;
3’b011: step1<=3’b100;
3’b100: step1<=3’b010;
3’b010: step1<=3’b000;
default:step1<=3’b000;
endcase
end
always @(negedge clkin )
begin
case (step2)
3’b000: step2<=3’b001;
3’b001: step2<=3’b011;
3’b011: step2<=3’b100;
3’b100: step2<=3’b010;
3’b010: step2<=3’b000;
default:step2<=3’b000;
endcase
end
assign clkout=step1[0]|step2[0];
endmodule
//十分频
module div_10(clkin,clkout);
input clkin;
output reg clkout;
reg[2:0]scan_cnt;
always@(posedge clkin)
begin
if(scan_cnt==3’b100)
begin
scan_cnt<=0;
clkout<=!clkout;
end
else
begin
scan_cnt<=scan_cnt+3’b1;
end
end
endmodule