module synFIFO(
input clk,rst_n,rd,wr,
input [7:0] data_in,
output [7:0] data_out,
output full,empty
);
reg [15:0] data_out;
reg [7:0] mem [15:0];
reg [3:0]rdp,wrp;
// mem + write pointer
always @(posedge clk)
if(!rst) wrp <= 0;
else (wr && !full) begin
wrp <= wrp + 1;
mem[wrp] <= data_in; end
// read pointer + data out
always @(posedge clk)
if(!rst) begin
rdp <= 0;
data_out <= 0; end
else if(rd && !empty) begin
rdp <= rdp + 1;
data_out <= mem[rdp]; end
// full 满信号的产生
always @(posedge clk)
if(!rst_n) full <= 0;
else if(rd && wr) ;
else if(rd) full <= 0;
else if(wr &&((wrp+1=rdp) || wrp=={
4{
1'b1}}&&rdp==0)) full <= 1;
// empty 空信号的产生
always @(posedge clk)
if(!rst_n) empty <= 0;
else if(rd && wr) ;
else if(wr) empty <= 0;
else if(rd &&((rdp+1=wrp) || rdp=={
4{
1'b1}}&&wrp==0)) empty <= 1;
endmodule
module asynFIFO(
input wclk,wrst_n,wr,
input [7:0] data_in,
input rclk,rrst_n,rd,
output [7:0] data_out,
output empty,full
);
reg [7:0] data_out;
reg [7:0]mem[15:0];
reg [3:0]wrp,rdp;
reg [3:0]wrp_grey1,wrp_grey2,rdp_grey1,rdp_grey2;
wire [3:0]wrp_grey0,rdp_grey0;
// write
always @(posedge wclk)
if(!wrst_n) wrp <= 0;
else if(!full && rd) begin
wrp <= wrp + 1;
mem[wrp] <= data_in; end
// read
always @(posedge rclk)
if(!rrst_n) rdp <= 0;
else if(!empty && rd) begin
rdp <= rdp + 1;
data_out <= mem[rdp]; end
// bin to grey
assign wrp_grey0 = wrp^(wrp>>1);
assign rdp_grey0 = rdp^(rdp>>1);
// 读写格雷码同步
always @(posedge wclk)
if(!wrst_n) begin
wrp_grey1 <= 0;
wrp_grey2 <= 0; end
else begin
wrp_grey1 <= wrp_grey0;
wrp_grey2 <= wrp_grey1; end
always @(posedge rclk)
if(!rrst_n) begin
rdp_grey1 <= 0;
rdp_grey2 <= 0; end
else begin
rdp_grey1 <= rdp_grey0;
rdp_grey2 <= rdp_grey1; end
// 空满信号的产生
assign empty == (wrp_grey2 == rdp_grey0)?1:0;
assign full == ({
~wrp_grey0[4:3],wrp_grey0[2:0]}=={
rdp_grey2[4:3],rdp_grey2[2:0]})?1:0;
endmodule