FPGA生成720P视频时钟

根据下面的时序图生成

`timescale 1ns / 1ps
module sdi_test(
	input clk_50M,
	input CLK27M,
	output GS2972_CLKO,
	output hs,
	output vs,
	output sdi_de,
	output[19:0] GS2972_DO,
	output GS2972_RATESEL0,
	output GS2972_RATESEL1,
	output GS2972_DE,
	output GS2972_RESET
    );
/***1280x720***/
parameter LinePeriod = 1650;//总的周期
parameter H_SyncPluse = 40;//HSYNC的时钟数
parameter H_BackPorch = 220;//前消隐
parameter H_ActivePix = 1280;//有效像素值
parameter H_FrontPorch = 110;//后消隐
parameter Hde_start = 260;//开始的时钟
parameter Hde_end = 1540;//结束的时钟

parameter FramePeriod = 750;//总的周期
parameter V_SyncPluse = 5;//VSYNC的时钟数
parameter V_BackPorch = 20;//
parameter V_ActivePix = 720;
parameter V_FrontPorch = 5;
parameter Vde_start = 25;
parameter Vde_end = 745;

reg[7:0] YUV_Y_reg;
reg[7:0] YUV_UV_reg;

reg[10:0] x_cnt = 0;
reg[10:0] y_cnt = 0;

reg hsync_r;
reg vsync_r;

reg hsync_de = 0;
reg vsync_de = 0;

reg[15:0] grid_data,grid_data1;
wire sdi_clk;

wire fPowerUp_Rst; // 得到复位波形 刚开始低，后面高
sSystemReset # (.MAX_COUNT(500000))
SystemReset
(
.iClk(CLK27M),
.iRst(1'b1),
.oRst(fPowerUp_Rst)
);

fpga_gclk sfpga_gclk
(
.CLK_IN1(clk_50M),      // IN

.CLK_OUT1(sdi_clk));    // OUT

//水平扫描计数
always @(posedge sdi_clk)
	if(x_cnt == LinePeriod) x_cnt <= 1;
	else x_cnt <= x_cnt + 1;

//水平扫描信号产生
always @(posedge sdi_clk)
	begin
		if(x_cnt == 1) hsync_r <= 1'b1;
		else if(x_cnt == H_SyncPluse) hsync_r <=1'b0;
	
		if(x_cnt == Hde_start) hsync_de <= 1'b1;
		else if(x_cnt == Hde_end) hsync_de <= 1'b0;
	end

//垂直扫描计数
always @(posedge sdi_clk)
	if(y_cnt == FramePeriod) y_cnt <= 1;
	else if(x_cnt == LinePeriod) y_cnt <= y_cnt + 1;

//垂直扫描信号产生
always @(posedge sdi_clk)
	begin
		if(y_cnt == 1) vsync_r <= 1'b1;
		else if(y_cnt == V_SyncPluse) vsync_r <=1'b0;
		
		if(y_cnt == Vde_start) vsync_de <= 1'b1;
		else if(y_cnt == Vde_end) vsync_de <= 1'b0;
	end
//图形产生

always @(negedge sdi_clk)
	begin
		//a<=(x_cnt[4] == 1'b1);
		//b<=(y_cnt[4] == 1'b1);
		if((x_cnt[4] == 1'b1)  | (y_cnt[4] == 1'b1))
			grid_data <= 16'h1080;//Y 00 的问题
		else
			grid_data <= 16'hff80;
	end
//图像赋值给寄存器
/* always @(posedge sdi_clk)
	if(hsync_de & vsync_de)
	begin
		YUV_Y_reg <= grid_data[15:8];
		YUV_UV_reg <= grid_data[7:0];
	end */


assign hs = hsync_r;
assign vs = vsync_r;
assign sdi_de = 1'b1;
//assign GS2972_DO[19:12] = (hsync_de & vsync_de)? YUV_Y_reg : 8'b00000000;
assign GS2972_DO[19:12] = grid_data[15:8];
assign GS2972_DO[1:0] = 2'b00;
assign GS2972_DO[11:10] = 2'b00;
assign GS2972_DO[9:2] = grid_data[7:0];
assign GS2972_DE = (hsync_de & vsync_de)? 1 : 0;
assign GS2972_CLKO = sdi_clk;
assign GS2972_RATESEL0 = 0;
assign GS2972_RATESEL1 = 0;
assign GS2972_RESET     = fPowerUp_Rst;
//assign YUV_V = (hsync_de & vsync_de)? YUV_V_reg : 4'b1111;


endmodule