在FPGA的开发过程中，必须进行RTL仿真来验证代码的功能是否正确。当我们在进行算法的开发时，算法需要有一定形式数据来激励才能验证其是否正确，比如开发FFT模块，输入一个sine信号来验证。直接使用verilog来生成这些测试信号比较麻烦，而matlab却很方便。使用matlab生成信号保存成txt，然后在testbench中读取，这样就完成了测试信号的产生。
1、在matlab中生成测试数据：
t=0: 5.0000e-06:1.5*10^-3;
y1=sin(2*pi*1000*t);
y2=sin(2*pi*40000*t);
y=y1+y2;
plot(t,y,'o');
yq = y*2^8; %手动量化，对比数据
yqr = floor(yq);
fid=fopen('sin.txt','w');
q=quantizer([10,8]); %关键的函数
N=length(t);
for i=1:N
z=num2bin(q,y(i));
fprintf(fid,'%s', z);
fprintf(fid,'\n');
end
fclose(fid)
2、在testbench中读取：
以下为主要功能代码，首先将txt文件装载到数组里，然后再生成数据和ready信号。
$readmemb("sin.txt",data,0,300);
$display("data is loaded");
reg [9:0] k;
reg [8:0] counter;
always @(posedge clk)
if(!rst_n) begin
ready <= 1'b0;
k <= 0;
counter <= 0;
din <= 0;
end
else
case(k)
0:begin
ready <= 1'b0;
din <= 10'd0;
k<= k+1;
counter <= 0;
end
1:begin
if(counter < 301)begin
counter <= counter + 1;
din <= data[counter];
k <=2;
ready <= 1'b1;
end
else begin
counter <= 0;
k <= 0;
din <= 0;
ready <= 1'b0;
end
end
2:begin
ready <= 1'b0;
din <= 0;
counter <= counter ;
k <= 1;
end
3:begin
ready <= 1'b0;
din <= 10'd0;
k<= 3;
counter <=0;
end
default:begin
ready <= 1'b0;
din <= 10'd0;
k<= 0;
counter <= 0;
end
endcase
3、将testbench的数据保存的txt文件中：
注意使用$siged将数据以有符号数写出
integer w_file;
initial w_file = $fopen("dataout.txt");
reg [8:0] m ;
always @ (posedge clk)
begin
if (!rst_n)
m <=0;
else if (valid&&m<=301)
m <= m+1;
else if(valid && m==302 )
m<=302；
end
reg valid_r;
always @ (posedge clk)
begin
if (!rst_n)
valid_r <=0;
else
valid_r <= valid;
end
reg [29:0] dout_r;
always @(posedge clk)
if(!rst_n)
dout_r <= 30'd0;
else
dout_r <= dout;
always @(m)
wait(valid_r==1)
begin
$fdisplay(w_file,"%d",$signed(dout_r));
if(m == 9'd301) //共写入301个数据
$stop;
$display("writing data into txt");
end
4、在matlab中读出testbench保存的数据
fid = fopen('dataout.txt','r');
for i = 1 : 301;
num(i) = fscanf(fid, '%d', 1); %从fid所指的文件以16进制方式读出一个数据。
end
fclose(fid);
plot(num,'o');
5、注意事项：
要将matlab生成的txt文件add 到sim的source里面，将仿真的数据保存到txt中时，当仿真关闭后才能生成数据，生成的txt文件在..\sim_1\behav\xsim下面