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# 1) Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs
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1 |
Introduction |
Multi-Clock design exits almost everywhere |
2 |
Metastability |
Dally and Poulton's Book |
3 |
Synchronizers |
Dally and Poulton's Book |
4 |
Static Timing Analysis |
1) What does STA do compared with Dynamic Verification |
5 |
Clock Naming Convertions |
identify clock source of signals by Naming Conventions |
6 |
Design Partitions |
1) one clock in one module |
7 |
Synthesis Scripts & Timing Analysis |
1) group modules of the same clock domain |
8 |
Synchroning Fast Signals into Slow clock domain |
Problem |
9 |
Passing Multiple Control Signals |
Problem |
10 |
Data-Path Synchronization |
Solution
|
11 |
FIFO Design |
|
12 |
Simulation Issues |
Disable timing checks of first-stage synchronizer flip-flop |
13 |
Conclusion |
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# 2) Simulation and Synthesis Techniques for Asynchronous FIFO Design
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1 |
Introduction |
|
2 |
Passing Multiple asynchronous signlas |
1. be used to passing multiple asynchronous signals |
3 |
Gray code counter - Style #1 |
|
4 |
Gray code counter - Style #2 |
|
5 |
Handling full & empty conditions |
1. full |
6 |
RTL code for FIFO Style #1 |
|
7 |
Comparing Binary and Gray code pointers |
binary advantage: |
8 |
Conclusion |
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# 3) Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
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1 |
Introduction |
|
2 |
Metastability |
|
3 |
Synchronizers |
Two synchronization scenarios |
4 |
Synchronizing fast signals into slow clock domains |
Solutions when missed samples are not allowed |
5 |
Passing multiple signals between clock domains |
Problem |
6 |
Naming conventions & design partitioning |
1) Use a clock naming convention to identify the clock source of every signal in a design.
|
7 |
Multi-clock gate-level simulation issues |
Problem |
8 |
Summary & conclusions |
1) Recommended 1-bit CDC techniques |