Notice on Synthesis and DFT commands
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# Syntheis
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1) how to add margin in timing constraint
10%_of_clock_period + additional_clock_uncertainty
2) path betwen asynchronous clock groups
set_max_delay is needed between some asynchronous clock groups
3) group_path for different path types sunch Input_to_Reg Reg_to_Reg
4) set_critical_range
5) LVT cells timing optimization
use "set target_library" to add LVT lib into target library
use "compile_ultra -incremental" to run increment compile
use "report_threshold_voltage_group" to review synthesis result
6) datapath synthsis review
report_resources
7) high-fanout nets review
report_net_fanout -high_fanout
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# DFT
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1) mutiple scan clock/reset are allowed in scan-chain synthesis
2) preview -testpoints can be useful
3) when MBIST is inserted, notice following
A) add SDC for MBIST during synthesis
B) set_scan_element false set_dont_touch attribute to MBIST
4) hierarchical scan
write_test_model
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# Other Useful Tcl Commands
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report_compile_options
checn_error -verbose
