verilog入门学习---项目导向---D9---2020/3/27

一、复数乘法器
算法：x=a+bi, y=c+di
x*y=(ac-bd)+(ad+bc)i
原理图：

代码实现：

module complex(a,b,c,d,out_real,out_im);
	input [3:0] a,b,c,d;
	output [8:0] out_real,out_im;
	wire [7:0] sub1,sub2,add1,add2;
//乘法
	mul_addtree U1(.a(a),.b(c),.out(sub1));
	mul_addtree U2(.a(b),.b(d),.out(sub2));
	mul_addtree U3(.a(a),.b(d),.out(add1));
	mul_addtree U4(.a(b),.b(c),.out(add2));
//加/减法
	assign out_real=sub1-sub2;
	assign out_im=add1+add2;
endmodule

module mul_addtree(a,b,out);
	input [3:0]a,b;
	output [7:0]out;
	wire [7:0]out;
	wire [7:0]stored0,stored1,stored2,stored3;
	wire [7:0]add01,add23;

	assign stored3=b[3]?{1'b0,a,3'b0}:8'b0;
	assign stored2=b[2]?{2'b0,a,2'b0}:8'b0;
	assign stored1=b[1]?{3'b0,a,1'b0}:8'b0;
	assign stored0=b[0]?{4'b0,a}:8'b0;

	assign add01=stored1+stored0;
	assign add23=stored2+stored3;
	assign out=add01+add23;
endmodule	

仿真结果：

二、有限冲激响应滤波器(FIR)
原理： 已输入样值的加权和形成输出
X[n]为输入序列，b0,b1…bn为抽头系数，当每个时钟的边沿到来时，采样值乘以抽头系数形成输出，（一个M阶的FIR有M+1个抽头系数）

原理图：

module FIR(Data_out,Data_in,clk,reset);
	output [9:0]Data_out;
	input [3:0]Data_in;
	input clock,reset;

	wire[3:0] shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8;
	shift_register U1(.Data_in(Data_in),.clk(clk),.reset(reset).shift_0(shift_0),.shift_1(shift_1),.shift_2(shift_2),.shift_3(shift_3),.shift_4(shift_4),.shift_5(shift_5),.shift_6(shift_6),.shift_7(shift_7),.shift_8(shift_8));
	caculator U2(.Data_in(Data_in),.clk(clk),.reset(reset).shift_0(shift_0),.shift_1(shift_1),.shift_2(shift_2),.shift_3(shift_3),.shift_4(shift_4),.shift_5(shift_5),.shift_6(shift_6),.shift_7(shift_7),.shift_8(shift_8));
endmodule

module shift_register(Data_in,clk,reset,shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8);
	input [3:0]Data_in;
	input clk,reset;
	output[3:0]shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8;
	reg [3:0]shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8;
always@(posedge clk or negedge clk)
begin
	if (reset)
	begin
		shift_0<=4'b0000;
		shift_1<=4'b0000;
		shift_2<=4'b0000;
		shift_3<=4'b0000;
		shift_4<=4'b0000;
		shift_5<=4'b0000;
		shift_6<=4'b0000;
		shift_7<=4'b0000;
		shift_8<=4'b0000;
	end
	else
	begin
		shift_0<=Data_in;
		shift_1<=shift_0;
		shift_2<=shift_1;
		shift_3<=shift_2;
		shift_4<=shift_3;
		shift_5<=shift_4;
		shift_6<=shift_5;
		shift_7<=shift_6;
		shift_8<=shift_7;
	end
end
endmodule

module caculator(shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8,Data_out);
	input[3:0]shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8;
	output[9:0]Data_out;
	wire[9:0]Data_out;
	wire [3:0]shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8;

FPGA（现场可编程门阵列，半定制的电路，查找表）的发展：
SOPC（可编程片上系统）




设计原则：

器件选型：