Error (10278): Verilog HDL Port Declaration error at **.v(21): input port "**" cannot be declared with type "<a variable data type, e.g. reg>" - 代码天地

Error (10278): Verilog HDL Port Declaration error at .v(21): input port "" cannot be declared with type "<a variable data type, e.g. reg>"

其他 2020-05-27 21:18:13 阅读次数: 0

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转载自www.cnblogs.com/linxionglei/p/12976566.html

Error (10278): Verilog HDL Port Declaration error at **.v(21): input port "**" cannot be declared with type "<a variable data type, e.g. reg>"

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