数电实验 可逆计数器设计
module yyc2018113559_3(clk,clr,x,Q,co,codeout);
input clk,clr,x;
output reg[6:0] codeout;
output co;
output reg[3:0] Q;
always @(posedge clk,negedge clr)
if(!clr)
Q<=4'd0;
else if(x)
begin
if(Q==4'd9)
Q<=4'd0;
else
Q<=Q+4'd1;
end
else
begin
if(Q==4'd0)
Q<=4'd9;
else
Q<=Q-4'd1;
end
assign co=(clr & ~x &Q==4'd0)|(x & Q==4'd9);
always @(clk)
begin
case(Q)
4'b0000:codeout=7'b1111110;
4'b0001:codeout=7'b0110000;
4'b0010:codeout=7'b1101101;
4'b0011:codeout=7'b1111001;
4'b0100:codeout=7'b0110011;
4'b0101:codeout=7'b1011011;
4'b0110:codeout=7'b1011111;
4'b0111:codeout=7'b1110000;
4'b1000:codeout=7'b1111111;
4'b1001:codeout=7'b1111011;
endcase
end
endmodule