练习demo:
LIBRARY IEEE; --38decoder
USE IEEE.std_logic_1164.ALL;
ENTITY decoder_38 IS
PORT(a,b,c,g1,g2a,g2b:IN std_logic;
y:OUT std_logic_vector(7 DOWNTO 0));
END decoder_38;
ARCHITECTURE behav OF decoder_38 IS
SIGNAL indata:std_logic_vector(2 DOWNTO 0);
BEGIN
indata<=c&b&a;
PROCESS(indata,g1,g2a,g2b)
BEGIN
IF(g1='1' and g2a='0' AND g2b='0')THEN
CASE indata IS
WHEN "000"=> y<="11111110";
WHEN "001"=> y<="11111101";
WHEN "010"=> y<="11111011";
WHEN "011"=> y<="11110111";
WHEN "100"=> y<="11101111";
WHEN "101"=> y<="11011111";
WHEN "110"=> y<="10111111";
WHEN "111"=> y<="01111111";
WHEN OTHERS => y<="XXXXXXXX";
END CASE;
ELSE
y<="11111111";
END IF;
END PROCESS;
END behav;
分频器:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY frequencies IS
PORT(clk_50M:IN std_logic;
clk_1:OUT std_logic);
END frequencies;
ARCHITECTURE behav OF frequencies IS
SIGNAL time:integer RANGE 0 TO 49999999;
SIGNAL m:integer RANGE 0 TO 1;
BEGIN
PROCESS(clk_50M)
BEGIN
IF rising_edge(clk_50M) THEN
time<=time+1;
IF m=0 THEN
clk_1<='1';
IF time=24999999 THEN
m<=1;
END IF;
ELSE
clk_1<='0';
IF time=49999999 THEN
m<=0;
time<=0;
END IF;
END IF;
END IF;
END PROCESS;
END behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity led is
port(led_out : out std_logic_vector(7 downto 0);
clk : in std_logic;
rst_n : in std_logic
);
end led;
architecture behavior of led is
signal light : std_logic_vector (7 downto 0);
begin
process(clk, rst_n)
begin
if(rst_n='0')then
light <= "00000010";
elsif(clk' event and clk='1')then
if(light = "00000000" ) then
light <= "00000001";
else
if(light = "10000000" ) then
light <= "00000001";
else
light <= light(6 downto 0)&'0';
end if;
end if;
end if;
end process;
led_out <= light;
end behavior;