二分频电路及代码

module cy4(
            input ext_clk_25m,  //外部输入25MHz时钟信号
            input ext_rst_n,    //外部输入复位信号，低电平有效
            output reg clk_12m5     //二分频时钟信号
        );

always @(posedge ext_clk_25m or negedge ext_rst_n)  
    if(!ext_rst_n) clk_12m5 <= 1'b0;
    else clk_12m5 <= ~clk_12m5;

endmodule