Verilog 十进制计数器

//单个计数器

module counter(clk,cin,cout,num,Rst_n);
input clk;//时钟
input cin;//待测量信号
input Rst_n;//复位键
output reg cout=0;//进位
output reg [3:0] num=0;//输出要显示数字,BCD码

always@(posedge cin or posedge clk or negedge Rst_n)
if(!Rst_n) num=0;
else if(clk) num=0;//一个周期内，有半个周期clk==0,故用0.5hz,周期2s,半周期1s
else if(num==9)begin
num<=0;cout<=1;
end
else begin
num<=num+1;cout<=0;
end

endmodule 

//6位十进制计数器

module counter_fre(clk_2,cin,cout,data,Rst_n);
input clk_2;//时钟2Hz
input cin;//待测信号
input Rst_n;//复位键
output reg cout;//溢出判断
output reg [23:0] data;//6位数字,BCD码

wire out;
wire [23:0] num;
wire cout_1,cout_2,cout_3,cout_4,cout_5;

counter(.clk(clk_2),.cin(cin),.cout(cout_1),.num(num[3:0]),.Rst_n(Rst_n));
counter(.clk(clk_2),.cin(cout_1),.cout(cout_2),.num(num[7:4]),.Rst_n(Rst_n));
counter(.clk(clk_2),.cin(cout_2),.cout(cout_3),.num(num[11:8]),.Rst_n(Rst_n));
counter(.clk(clk_2),.cin(cout_3),.cout(cout_4),.num(num[15:12]),.Rst_n(Rst_n));
counter(.clk(clk_2),.cin(cout_4),.cout(cout_5),.num(num[19:16]),.Rst_n(Rst_n));
counter(.clk(clk_2),.cin(cout_5),.cout(out),.num(num[23:20]),.Rst_n(Rst_n));

always@(posedge clk_2 or negedge Rst_n)begin
if(!Rst_n) data<=0;
else
data<=num;
end

always@(posedge clk_2 or negedge Rst_n)begin
cout=out;
end       

endmodule