linux下的EDA——DC使用

Design Compiler的作用是将RTL级代码转化为门级网表，为后续的时序分析和后仿做准备，其过程主要包括translation、optimization和mapping。DC的实现有两种方式，一种是命令行或脚本的方式，另外一种是图形界面方式。

DC综合需要库的支持，一般我们使用的库为.db的二进制文件。

库分为三个等级：target library、link library和symbol library。target library是指RTL级的HDL描述到门级时所需的标准单元综合库，它是由芯片制造商（Foundry）提供的，包含了物理信息的单元模型。link library可以是同target_library一样的单元库，也可以是已经底层已经被综合到门级的模块，在由下而上的综合过程中，上一层的设计调用底层已综合模块时，将从link_library中寻找并链接起来。symbol library是显示电路时，用于标识器件、单元的库。芯片供应商提供的库通常有max,type,min三种类型，代表操作环境为最坏(worst)，典型(type)，最好(best)三种情况，当然也有其他形式的库如fast.db、slow.db等。

DC综合中还要进行静态时序分析，这一点在很多教程中都有讲解，就不在赘述。需要记得的就是在DC中需要进行时序约束，与在其他软件.sdc中所写约束基本一致。

1.简单的命令行demo（学校实验教程）

linux系统为openSUSE，软件版本为DC2013

待综合代码文件为gray_counter.v，模块名为graycount，初始代码为：

// MODULE: Sequential Circuit Example: gray_counter.v 
// MODULE DECLARATION 
module graycount (gcc_out, reset_n, clk, en_count); 
output [2-1:0] gcc_out; // current value of counter 
input reset_n; // active-low RESET signal 
input clk; // clock signal 
input en_count; // counting is enabled when en_count = 1 
// SIGNAL DECLARATIONS 
reg [2-1:0] gcc_out; 
// Compute new gcc_out value based on current gcc_out value 
always @(negedge reset_n or posedge clk) begin 
if (~reset_n) 
gcc_out <= 2'b00; 
else begin // MUST be a (posedge clk) - don't need “else if (posedge clk)" 
if (en_count) begin // check the count enable 
case (gcc_out) 
2'b00: begin gcc_out <= 2'b01; end 
2'b01: begin gcc_out <= 2'b11; end 
2'b11: begin gcc_out <= 2'b10; end 
default: begin gcc_out <= 2'b00; end 
endcase // of case 
end // of if (en_count) 
end // of else 
end // of always loop for computing next gcc_out value 
endmodule

该.v文件在综合后会被覆写。

新建文件夹dc，将gray_counter.v文件复制入此文件夹。

在确保DC已经正确安装的前提下，右键打开终端

开始输入指令：

dc_shell-xg-t

打开dc，此时命令行前会变为

dc_shell>

形式

输入指令（dc_shell> 不是输入的）

dc_shell> define_design_lib WORK -path "work"

这个是DC内部命令格式，启动DC时的路径，也就是DC工作时的路径，

下面显示"1"时执行完成

dc_shell> set target_library [ list /home/tshell/lib/TSMC90/fast.db]

指定target_library的路径和库，根据自己系统中的位置修改

dc_shell> set link_library "* $target_library"

指定link_library等同于target_library

dc_shell> analyze -library WORK -format verilog gray_counter.v

这句里面填要综合的.v文件

dc_shell> elaborate -architecture verilog -library WORK graycount

这句里 graycount 是顶层模块

dc_shell> check_design

检查设计是否有错

此时终端中全部内容为：

tshell@tshell:~/gao_test/dc> dc_shell-xg-t

                      Design Compiler Graphical
                            DC Ultra (TM)
                             DFTMAX (TM)
                         Power Compiler (TM)
                           DesignWare (R)
                           DC Expert (TM)
                         Design Vision (TM)
                          HDL Compiler (TM)
                         VHDL Compiler (TM)
                            DFT Compiler
                        Library Compiler (TM)
                         Design Compiler(R)

          Version H-2013.03-SP1 for RHEL64 -- Apr 21, 2013
               Copyright (c) 1988-2013 Synopsys, Inc.

This software and the associated documentation are confidential and 
proprietary to Synopsys, Inc. Your use or disclosure of this software 
is subject to the terms and conditions of a written license agreement 
between you, or your company, and Synopsys, Inc.

Initializing...
dc_shell> define_design_lib WORK -path "work"
1
dc_shell> set target_library [ list /home/tshell/lib/TSMC90/fast.db]
/home/tshell/lib/TSMC90/fast.db
dc_shell> set link_library "* $target_library"
* /home/tshell/lib/TSMC90/fast.db
dc_shell> analyze -library WORK -format verilog gray_counter.v
Running PRESTO HDLC
Searching for ./gray_counter.v
Compiling source file ./gray_counter.v
Presto compilation completed successfully.
Loading db file '/home/tshell/lib/TSMC90/fast.db'
1
dc_shell> elaborate -architecture verilog -library WORK graycount
Loading db file '/home/tshell/programs/synopsys/design_compiler_2013/libraries/syn/gtech.db'
Loading db file '/home/tshell/programs/synopsys/design_compiler_2013/libraries/syn/standard.sldb'
  Loading link library 'fast'
  Loading link library 'gtech'
Running PRESTO HDLC

Statistics for case statements in always block at line 11 in file
    './gray_counter.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            16            |    auto/auto     |
===============================================

Inferred memory devices in process
    in routine graycount line 11 in file
        './gray_counter.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     gcc_out_reg     | Flip-flop |   2   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Elaborated 1 design.
Current design is now 'graycount'.
1
dc_shell> check_design
1

接下来设置约束

dc_shell> create_clock clk -name ideal_clock1 -period 5

产生时钟

dc_shell> set_input_delay 2.0 [remove_from_collection [all_inputs] clk] -clock ideal_clock1

时钟输入延时

dc_shell> set_output_delay 2.0 [all_outputs] -clock ideal_clock1

时钟输出延时

dc_shell> set_max_area 0

预期的最大面积，这里设置为0意味着希望面积无穷小

dc_shell> compile -map_effort medium -area_effort medium

为优化面积而做出的努力程度

此时显示信息

dc_shell> create_clock clk -name ideal_clock1 -period 5
1
dc_shell> set_input_delay 2.0 [remove_from_collection [all_inputs] clk] -clock ideal_clock1
1
dc_shell> set_output_delay 2.0 [all_outputs] -clock ideal_clock1
1
dc_shell> set_max_area 0
1
dc_shell> compile -map_effort medium -area_effort medium
Information: Evaluating DesignWare library utilization. (UISN-27)

============================================================================
| DesignWare Building Block Library  |         Version         | Available |
============================================================================
| Basic DW Building Blocks           | H-2013.03-DWBB_201303.1 |     *     |
| Licensed DW Building Blocks        |                         |           |
============================================================================



  Beginning Pass 1 Mapping
  ------------------------
  Processing 'graycount'

  Updating timing information
Information: Updating design information... (UID-85)

  Beginning Mapping Optimizations  (Medium effort)
  -------------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:01      62.1      0.00       0.0       0.0                          
    0:00:01      62.1      0.00       0.0       0.0                          
    0:00:01      62.1      0.00       0.0       0.0                          
    0:00:01      62.1      0.00       0.0       0.0                          
    0:00:01      62.1      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          



  Beginning Delay Optimization Phase
  ----------------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:01      45.2      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          


  Beginning Area-Recovery Phase  (max_area 0)
  -----------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
    0:00:02      44.5      0.00       0.0       0.0                          
Loading db file '/home/tshell/lib/TSMC90/fast.db'

  Optimization Complete
  ---------------------
1

设置文件输出

dc_shell> report_area >  synth_area.rpt

写出面积信息到synth_area.rpt

dc_shell> report_cell >  synth_cells.rpt

dc_shell> report_qor >  synth_qor.rpt

dc_shell> report_resources >  synth_resoutces.rpt

dc_shell> report_timing -max_paths 10 >  synth_timing.rpt

写出关键路径最长的10条路径

dc_shell> write_sdc gray_counter.sdc

写出sdc时序约束

dc_shell> write -f ddc -hierarchy -output gray_counter.ddc

dc_shell> write -hierarchy -format verilog -output gray_counter.v

覆盖.v文件

此时显示信息

dc_shell> report_area >  synth_area.rpt
dc_shell> report_cell >  synth_cells.rpt
dc_shell> report_qor >  synth_qor.rpt
dc_shell> report_resources >  synth_resoutces.rpt
dc_shell> report_timing -max_paths 10 >  synth_timing.rpt
dc_shell> write_sdc gray_counter.sdc
1
dc_shell> write -f ddc -hierachy -output gray_counter.ddc
Error: unknown option '-hierachy' (CMD-010)
dc_shell> write -f ddc -hierarchy -output gray_counter.ddc
Writing ddc file 'gray_counter.ddc'.
1
dc_shell> write -hierarchy -format verilog -output gray_counter.v
Writing verilog file '/home/tshell/gao_test/dc/gray_counter.v'.
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
1

指令操作结束，此时可以从相关文件中获取各种信息。

2.脚本方式

脚本方式实际上就是把命令行写入脚本中，然后运行脚本即可。

在文件夹中新建go.tcl，打开后将命令行复制入

set synopsys_dc_setup_file 0

if { $synopsys_dc_setup_file == 0} {
set target_library [ list /home/tshell/lib/TSMC90/fast.db]

set link_library "* $target_library"}

define_design_lib WORK -path "work"

analyze -library WORK -format verilog gray_counter.v

elaborate -architecture verilog -library WORK graycount

check_design

create_clock clk -name ideal_clock1 -period 5

set_input_delay 2.0 [remove_from_collection [all_inputs] clk] -clock ideal_clock1

set_output_delay 2.0 [all_outputs] -clock ideal_clock1

set_max_area 0

compile -map_effort medium -area_effort medium

report_area >  synth_area.rpt
report_cell >  synth_cells.rpt
report_qor >  synth_qor.rpt
report_resources >  synth_resoutces.rpt
report_timing -max_paths 10 >  synth_timing.rpt
write_sdc gray_counter.sdc

write -f ddc -hierarchy -output gray_counter.ddc

write -hierarchy -format verilog -output gray_counter.v

报错，退出。右键打开终端，输入

dc_shell

等待开启，之后输入

source go.tcl

即可得到与之前相同结果。

linux下的EDA——DC使用

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