基础：由PC通过UART发送数据在VGA显示。数据可以为字母，数字，汉字(任选10个字)，VGA分为左右两个区域，输入字母或者数字时在VGA左边显示，输入汉字时在VGA右边显示。
发挥：有删除功能，可通过按键删除显示的数字，字母或者汉字。左边的按键按下字母或者数字删除，右边的按键按下汉字删除。每次仅可删除一个字符。举例：VGA左侧显示FPGA 时，按下左边的键，VGA显示FPG，再按一下，显示FP。
这个思想其实很简单：
大致三个模块：
1、串口通信的接收端模块
2、字符的缓冲区
3、qvga显示屏的驱动模块
但是实现起来却不是很容易
首先我们可以知道qvga其实显示的话和数码管的显示原理差不多，这里只不过把屏幕看做一个二维的数组在每个位置写0或者1标志显示的字模。通过bgr通道进行调色。
但是这里的关键点在于如何读取到这样一个内存区域的数据
这里我想到了两个方法但是感觉工程量都很大，让我跟大家扯一下：
1、利用ip核生成一些ROM模块用于存储这几个字符的数据，然后在PC串口发送后接收到不同的标志信号然后在不同的区域读取相应的字符数据
这个方法比较省定义字符缓冲区（我自己随便叫的，就是用于存取字符的地方）的工程量，但是在不同的地方进行读取的时候觉得工程量也不小，而且自己思路比较迷没有想好如何处理，尤其是在发挥部分删除的时候，觉得思路和第二种差不多甚至更麻烦所以我个人处理的办法是第二种。
2、直接写一个字符存储的区域当接收处理端，当收到相应的字符时将相应的值传到寄存器中，然后在显示屏幕的中固定读取相应位置的数据实现字符的显示。
这里其实qvga和uart的模块早就调试好了主要问题出现在字符缓冲区中，各种小bug，真是有点让人头大·····
个人觉得自己的这个方法有点蠢，，菜鸟级别的，缺点：
1、只能显示确定的大小是字符
2、存储空间太小
3、浪费了大量的寄存器
高人指点说存储器可以用ram进行动态处理，过段时间看看ram看自己可不可以升级下自己这个蠢方案。
大致思路就是这样了：
利用发送完成位进行判断数据是否是想要的将数据写入一系列 reg中qvga模块中返回一个算是地址进行对y行扫描的时候进行寻址查码
暂时更新一份只可以读英文和数字的代码，明天估计就可以把余下的功能完善了
top.v:
module top(ext_clk_25m,ext_rst_n,uart_rx,
lcd_light_en,lcd_clk,lcd_hsy,lcd_vsy,
lcd_r,lcd_g,lcd_b
);
input ext_clk_25m;
input ext_rst_n;
input uart_rx;
output lcd_light_en;
output lcd_clk;
output lcd_hsy;
output lcd_vsy;
output [4:0] lcd_r;
output [5:0] lcd_g;
output [4:0] lcd_b;
wire [7:0]data_byte;
wire rxd_finish;
wire rxd_state;
wire [79:0]data_db;
wire [79:0]data_db_han;
wire [3:0]data_ab;
//接收模块
rxd uut_rxd(
.clk(ext_clk_25m),
.rst_n(ext_rst_n),
.bps_set(2'd1),
.rxd(uart_rx),
.data_byte(data_byte),
.rxd_finish(rxd_finish),
.uart_state(rxd_state)
);
//英文数字字符缓冲区
dat_buf uut_dat_buf(
.clk(ext_clk_25m),
.rst_n(ext_rst_n),
.data_db_chars(data_db),
.data_byte(data_byte),
.rxd_finish(rxd_finish),
.data_ab(data_ab)
);
//汉字字符缓冲区
dat_buf_han uut_dat_buf_han(
.clk(ext_clk_25m),
.rst_n(ext_rst_n),
.data_db_chars(data_db_han),
.data_byte(data_byte),
.rxd_finish(rxd_finish),
.rxd_state(rxd_state),
.data_ab(data_ab)
);
//qvga显示模块
lcd_controller uut_lcd_conreoller(
.clk(ext_clk_25m),
.rst_n(ext_rst_n),
.lcd_light_en(lcd_light_en),
.lcd_clk(lcd_clk),
.lcd_hsy(lcd_hsy),
.lcd_vsy(lcd_vsy),
.lcd_r(lcd_r),
.lcd_g(lcd_g),
.lcd_b(lcd_b),
.data_db(data_db),
.data_ab(data_ab),
.data_db_han(data_db_han)
);
endmoduleqvga_controller.v:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:05:59 01/20/2019
// Design Name:
// Module Name: lcd_controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lcd_controller(clk,rst_n,lcd_light_en,lcd_clk,lcd_hsy,lcd_vsy,lcd_r,lcd_g,lcd_b,data_db,data_ab,data_db_han
);
input clk;
input rst_n;
input [79:0] data_db;
input [79:0] data_db_han;
output [3:0]data_ab;
output lcd_light_en;
output lcd_clk;
output reg lcd_hsy;
output reg lcd_vsy;
output [4:0] lcd_r;
output [5:0] lcd_g;
output [4:0] lcd_b;
parameter HSY_TH=9'D408-1'D1;//周期
parameter HSY_THS=9'D30 ;//脉冲宽度
parameter HSY_THB=9'D38 ;//后沿
parameter HSY_TEP=9'D320 ;//显示周期
parameter HSY_THE=9'D68 ;//同步周期
parameter HSY_THF=9'D20 ;//前沿
parameter VSY_TV=9'D262-1'D1;//周期
parameter VSY_TVS=9'D3 ;//脉冲宽度
parameter VSY_TVB=9'D15 ;//后沿
parameter VSY_TVD=9'D240 ;//显示周期
parameter VSY_TVF=9'D4 ;//前沿
//lcd背光常开
assign lcd_light_en=1'b1;
//配置驱动时钟6.25mHz
reg [1:0] lcd_cnt;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
lcd_cnt<=1'b0;
end
else begin
lcd_cnt<=lcd_cnt+1'b1;
end
end
assign lcd_clk=lcd_cnt[1];
wire dchange ={lcd_cnt==2'd2};
//X和Y轴计数器
reg[8:0] xcnt;
reg[8:0] ycnt;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
xcnt<=1'b0;
end
else if(dchange==1'b1)begin
if(xcnt==HSY_TH)begin
xcnt<=1'b0;
end
else begin
xcnt<=xcnt+1'b1;
end
end
else;
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
ycnt<=1'b0;
end
else if(dchange&&xcnt==HSY_TH)begin
if(ycnt==VSY_TV)begin
ycnt<=1'b0;
end
else begin
ycnt<=ycnt+1'b1;
end
end
else begin
ycnt<=ycnt;
end
end
//lcd显示的有效区域
reg valid;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
valid<=1'b0;
end
else if(ycnt>=(VSY_TVS+VSY_TVB)&&ycnt<(VSY_TVS+VSY_TVB+VSY_TVD)&&
xcnt>=(HSY_THS+HSY_THB)&&xcnt<(HSY_TEP+HSY_THB+HSY_THE))begin
valid<=1'b1;
end
else begin
valid<=1'b0;
end
end
//LCD驱动行场同步信号产生逻辑
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
lcd_hsy<=1'b1;
end
else if(xcnt==1'b0)begin
lcd_hsy<=1'b0;
end
else if(xcnt>=HSY_THS)begin
lcd_hsy<=1'b1;
end
else begin
lcd_hsy<=lcd_hsy;
end
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
lcd_vsy<=1'b1;
end
else if(ycnt==1'b0)begin
lcd_vsy<=1'b0;
end
else if(ycnt>=VSY_TVS)begin
lcd_vsy<=1'b1;
end
else begin
lcd_vsy<=lcd_vsy;
end
end
assign data_ab = ycnt-5'd18;
reg [8:0]tmp_cnt;
reg [8:0]tmp_cnt_0;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
tmp_cnt<=1'b0;
tmp_cnt_0<=1'b0;
end
else if(valid==1'b0)begin
tmp_cnt<=1'b0;
tmp_cnt_0<=1'b0;
end
else if(xcnt>=(HSY_THS+HSY_THB)&&xcnt<(HSY_THS+HSY_THB+9'd80)&&dchange)begin
tmp_cnt<=tmp_cnt+1'b1;
end
else if(xcnt>=((HSY_TEP/2'd2)+HSY_THS+HSY_THB)&&xcnt<((HSY_TEP/2'd2)+HSY_THS+HSY_THB+9'd80)&&dchange)begin
tmp_cnt_0<=tmp_cnt_0+1'b1;
end
else begin
tmp_cnt<=tmp_cnt;
tmp_cnt_0<=tmp_cnt_0;
end
end
reg [15:0]lcd_db_rgb;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
lcd_db_rgb<=16'd0;
end
else if(xcnt==(HSY_TEP/2+HSY_THB+HSY_THS))begin
lcd_db_rgb[10:5]<=6'd63;
end
else if(ycnt>=(VSY_TVS+VSY_TVB)&&ycnt<(VSY_TVS+VSY_TVB+9'd16)
&&xcnt>=(HSY_THS+HSY_THB)&&xcnt<(HSY_THS+HSY_THB+9'd80))begin
if(dchange)begin //英文字符区域
if(data_db[tmp_cnt]==1'b1)begin
lcd_db_rgb<=16'h001f;
end
else begin
lcd_db_rgb<=16'hf800;
end
end
else;
end
else if(ycnt>=(VSY_TVS+VSY_TVB)&&ycnt<(VSY_TVS+VSY_TVB+9'd16)
&&xcnt>(HSY_TEP/2+HSY_THS+HSY_THB)&&xcnt<(HSY_TEP/2+HSY_THS+HSY_THB+9'd80))begin
if(dchange)begin //中文字符区域
if(data_db_han[tmp_cnt_0]==1'b1)begin
lcd_db_rgb<=16'h001f;
end
else begin
lcd_db_rgb<=16'hf800;
end
end
else;
end
else begin
lcd_db_rgb<=1'b0;
end
end
assign lcd_r =valid ? lcd_db_rgb[15:11]:5'd0;
assign lcd_g =valid ? lcd_db_rgb[10:5]:6'd0;
assign lcd_b =valid ? lcd_db_rgb[4:0]:5'd0;
endmodule
rxd.v:
module rxd(clk,rst_n,bps_set,rxd,data_byte,rxd_finish,uart_state
);
input clk ;//输入时钟
input rst_n ;//复位信号
input [1:0] bps_set ;//波特率选择
input rxd ;//接收模块
output [7:0] data_byte ;//接收数据
output rxd_finish;//发送完成标志
output uart_state;//串口通信状态
reg [7:0] data_byte ;
reg rxd_finish;
reg uart_state;
parameter BPS_4800 =16'd324,
BPS_9600 =16'd162,
BPS_19200 =16'd80 ,
BPS_115200 =16'd13 ;
//消除亚稳态
reg rxd_s0,rxd_s1; //同步寄存器
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
rxd_s0<=1'b0;
rxd_s1<=1'b0;
end
else begin
rxd_s0<=rxd;
rxd_s1<=rxd_s0;
end
end
reg rxd_temp0,rxd_temp1;//数据寄存器
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
rxd_temp0<=1'b0;
rxd_temp1<=1'b0;
end
else begin
rxd_temp0<=rxd_s1;
rxd_temp1<=rxd_temp0;
end
end
wire rxd_negedge =~rxd_temp0&rxd_temp1;
reg [15:0] div_cnt;
reg [15:0] time_div;
//波特率选择模块
always@(*)begin
if(rst_n==1'b0)begin
time_div=BPS_9600;
end
else begin
case(bps_set)
2'b00: time_div = BPS_4800;
2'b01: time_div = BPS_9600;
2'b10: time_div = BPS_19200;
2'b11: time_div = BPS_115200;
default:time_div = BPS_9600;
endcase
end
end
//波特率计数模块
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
div_cnt<=1'b0;
end
else if(uart_state==1'b1)begin
if(div_cnt==time_div)begin
div_cnt<=1'b0;
end
else begin
div_cnt<=div_cnt+1'b1;
end
end
else begin
div_cnt<=1'b0;
end
end
//波特率时钟模块
reg bps_clk;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
bps_clk<=1'b0;
end
else if(div_cnt==time_div)begin
bps_clk<=1'b1;
end
else begin
bps_clk<=1'b0;
end
end
//bps计数模块
reg [7:0] bps_cnt;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
bps_cnt<=8'd0;
end
else if(rxd_finish==1'b1||(bps_cnt==8'd12 && (Start>3'd3)))begin
bps_cnt<=8'd0;
end
else if(bps_clk==1'b1)begin
bps_cnt<=bps_cnt+1'b1;
end
else begin
bps_cnt<=bps_cnt;
end
end
always@(*)begin
if(rst_n==1'b0)begin
rxd_finish<=1'b0;
end
else if(bps_cnt==8'd159)begin
rxd_finish<=1'b1;
end
else begin
rxd_finish<=1'b0;
end
end
//数据缓冲区模块
reg [2:0] r_data_byte[7:0];
reg [2:0]Start,Stop;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
Start<=3'd0;
r_data_byte[0]<=3'd0;
r_data_byte[1]<=3'd0;
r_data_byte[2]<=3'd0;
r_data_byte[3]<=3'd0;
r_data_byte[4]<=3'd0;
r_data_byte[5]<=3'd0;
r_data_byte[6]<=3'd0;
r_data_byte[7]<=3'd0;
Stop<=3'd0;
end
else if(bps_clk==1'b1)begin
if(bps_cnt==1'b0)begin
Start<=3'd0;
r_data_byte[0]<=3'd0;
r_data_byte[1]<=3'd0;
r_data_byte[2]<=3'd0;
r_data_byte[3]<=3'd0;
r_data_byte[4]<=3'd0;
r_data_byte[5]<=3'd0;
r_data_byte[6]<=3'd0;
r_data_byte[7]<=3'd0;
Stop<=3'd0;
end
if(16'd6<=bps_cnt&&bps_cnt<=16'd12)begin
Start<=Start+rxd_s1;
end
else if(16'd22<=bps_cnt&&bps_cnt<=16'd28)begin
r_data_byte[0]<=r_data_byte[0]+rxd_s1;
end
else if(16'd38<=bps_cnt&&bps_cnt<=16'd44)begin
r_data_byte[1]<=r_data_byte[1]+rxd_s1;
end
else if(16'd54<=bps_cnt&&bps_cnt<=16'd60)begin
r_data_byte[2]<=r_data_byte[2]+rxd_s1;
end
else if(16'd70<=bps_cnt&&bps_cnt<=16'd76)begin
r_data_byte[3]<=r_data_byte[3]+rxd_s1;
end
else if(16'd86<=bps_cnt&&bps_cnt<=16'd92)begin
r_data_byte[4]<=r_data_byte[4]+rxd_s1;
end
else if(16'd102<=bps_cnt&&bps_cnt<=16'd108)begin
r_data_byte[5]<=r_data_byte[5]+rxd_s1;
end
else if(16'd118<=bps_cnt&&bps_cnt<=16'd124)begin
r_data_byte[6]<=r_data_byte[6]+rxd_s1;
end
else if(16'd134<=bps_cnt&&bps_cnt<=16'd140)begin
r_data_byte[7]<=r_data_byte[7]+rxd_s1;
end
else if(16'd150<=bps_cnt&&bps_cnt<=16'd156)begin
Stop<=Stop+rxd_s1;
end
end
else;
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
data_byte<=8'd0;
end
else if(bps_cnt==8'd159)begin
data_byte[0]<=(r_data_byte[0]>3'd3)?1'b1:1'b0;
data_byte[1]<=(r_data_byte[1]>3'd3)?1'b1:1'b0;
data_byte[2]<=(r_data_byte[2]>3'd3)?1'b1:1'b0;
data_byte[3]<=(r_data_byte[3]>3'd3)?1'b1:1'b0;
data_byte[4]<=(r_data_byte[4]>3'd3)?1'b1:1'b0;
data_byte[5]<=(r_data_byte[5]>3'd3)?1'b1:1'b0;
data_byte[6]<=(r_data_byte[6]>3'd3)?1'b1:1'b0;
data_byte[7]<=(r_data_byte[7]>3'd3)?1'b1:1'b0;
end
else begin
data_byte<=data_byte;
end
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
uart_state<=1'b0;
end
else if(rxd_negedge==1'b1)begin
uart_state<=1'b1;
end
else if(rxd_finish==1'b1||(bps_cnt==8'd12 && (Start>3'd3)))begin
uart_state<=1'b0;
end
else begin
uart_state<=uart_state;
end
end
endmodule英文字符识别模块：dat_buf.v
module dat_buf(clk,rst_n,data_db_chars,data_byte,rxd_finish,data_ab
);
input clk;
input rst_n;
input [7:0]data_byte;
input rxd_finish;
input [3:0] data_ab;
output reg [79:0]data_db_chars;
reg [127:0]data_db;
reg char1;
parameter S0 =4'D0 ,
S1 =4'D1 ,
S2 =4'D2 ,
S3 =4'D3 ,
S4 =4'D4 ,
S5 =4'D5 ,
S6 =4'D6 ,
S7 =4'D7 ,
S8 =4'D8 ,
S9 =4'D9 ,
S10=4'D10,
CHARS_1 =128'H000000E7424222242414141808080000,/*V*/
CHARS_2 =128'H00000000000000634242424262DC0000,//u
CHARS_3 =128'H0000003C4242424020100804427E0000,//2
CHARS_4 =128'H0000000003020272120A0E1222770000,//k
CHARS_5 =128'H000000000000003C42424242423C0000;//o
reg char;
reg finish_0;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
char<=1'b0;
finish_0<=1'b0;
end
else begin
finish_0<=rxd_finish;
char<=char1;
end
end
reg full_flag;
//英文字符模块
always@(*)begin
if(rst_n==1'b0)begin
data_db=1'b0;
char1=1'b0;
end
else if(finish_0==1'b0||full_flag==1'b1)begin
data_db=data_db;
char1=1'b0;
end
else if(data_byte=="V")begin
data_db=CHARS_1;
char1=1'd1;
end
else if(data_byte=="u")begin
data_db=CHARS_2;
char1=1'd1;
end
else if(data_byte=="2")begin
data_db=CHARS_3;
char1=1'd1;
end
else if(data_byte=="k")begin
data_db=CHARS_4;
char1=1'd1;
end
else if(data_byte=="o")begin
data_db=CHARS_5;
char1=1'd1;
end
else begin
data_db=data_db;
char1=1'b0;
end
end
reg [79:0]data_db_char[15:0];
//状态转换
reg [3:0] state_c;
reg [3:0] state_n;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
state_c<=S0;
end
else begin
state_c<=state_n;
end
end
always@(*)begin
if(rst_n==1'b0)begin
state_n=S0;
end
else begin
case(state_c)
S0:if(char1==1'b1)begin
state_n=S1;
end
else begin
state_n=S0;
end
S1:if(char1==1'b1)begin
state_n=S2;
end
else begin
state_n=S1;
end
S2:if(char1==1'b1)begin
state_n=S3;
end
else begin
state_n=S2;
end
S3:if(char1==1'b1)begin
state_n=S4;
end
else begin
state_n=S3;
end
S4:if(char1==1'b1)begin
state_n=S5;
end
else begin
state_n=S4;
end
S5:if(char1==1'b1)begin
state_n=S6;
end
else begin
state_n=S5;
end
S6:if(char1==1'b1)begin
state_n=S7;
end
else begin
state_n=S6;
end
S7:if(char1==1'b1)begin
state_n=S8;
end
else begin
state_n=S7;
end
S8:if(char1==1'b1)begin
state_n=S9;
end
else begin
state_n=S8;
end
S9:if(char1==1'b1)begin
state_n=S10;
end
else begin
state_n=S9;
end
S10:
state_n=S10;
default:state_n=S0;
endcase
end
end
//输出模块
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
full_flag=1'b0;
end
else if(state_c==S10)begin
full_flag=1'b1;
end
else begin
full_flag=1'b0;
end
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
data_db_char[0] =1'b0;
data_db_char[1] =1'b0;
data_db_char[2] =1'b0;
data_db_char[3] =1'b0;
data_db_char[4] =1'b0;
data_db_char[5] =1'b0;
data_db_char[6] =1'b0;
data_db_char[7] =1'b0;
data_db_char[8] =1'b0;
data_db_char[9] =1'b0;
data_db_char[10]=1'b0;
data_db_char[11]=1'b0;
data_db_char[12]=1'b0;
data_db_char[13]=1'b0;
data_db_char[14]=1'b0;
data_db_char[15]=1'b0;
end
else if(char==1'b0)begin
data_db_char[0] =data_db_char[0] ;
data_db_char[1] =data_db_char[1] ;
data_db_char[2] =data_db_char[2] ;
data_db_char[3] =data_db_char[3] ;
data_db_char[4] =data_db_char[4] ;
data_db_char[5] =data_db_char[5] ;
data_db_char[6] =data_db_char[6] ;
data_db_char[7] =data_db_char[7] ;
data_db_char[8] =data_db_char[8] ;
data_db_char[9] =data_db_char[9] ;
data_db_char[10]=data_db_char[10];
data_db_char[11]=data_db_char[11];
data_db_char[12]=data_db_char[12];
data_db_char[13]=data_db_char[13];
data_db_char[14]=data_db_char[14];
data_db_char[15]=data_db_char[15];
end
else if(state_c==S1)begin
data_db_char[15][7:0]=data_db[7:0];
data_db_char[14][7:0]=data_db[15:8];
data_db_char[13][7:0]=data_db[23:16];
data_db_char[12][7:0]=data_db[31:24];
data_db_char[11][7:0]=data_db[39:32];
data_db_char[10][7:0]=data_db[47:40];
data_db_char[9] [7:0]=data_db[55:48];
data_db_char[8] [7:0]=data_db[63:56];
data_db_char[7] [7:0]=data_db[71:64];
data_db_char[6] [7:0]=data_db[79:72];
data_db_char[5] [7:0]=data_db[87:80];
data_db_char[4] [7:0]=data_db[95:88];
data_db_char[3] [7:0]=data_db[103:96];
data_db_char[2] [7:0]=data_db[111:104];
data_db_char[1] [7:0]=data_db[119:112];
data_db_char[0] [7:0]=data_db[127:120];
end
else if(state_c==S2)begin
data_db_char[15][15:8]=data_db[7:0];
data_db_char[14][15:8]=data_db[15:8];
data_db_char[13][15:8]=data_db[23:16];
data_db_char[12][15:8]=data_db[31:24];
data_db_char[11][15:8]=data_db[39:32];
data_db_char[10][15:8]=data_db[47:40];
data_db_char[9][15:8] =data_db[55:48];
data_db_char[8][15:8] =data_db[63:56];
data_db_char[7][15:8] =data_db[71:64];
data_db_char[6][15:8] =data_db[79:72];
data_db_char[5][15:8] =data_db[87:80];
data_db_char[4][15:8] =data_db[95:88];
data_db_char[3][15:8] =data_db[103:96];
data_db_char[2][15:8] =data_db[111:104];
data_db_char[1][15:8] =data_db[119:112];
data_db_char[0][15:8] =data_db[127:120];
end
else if(state_c==S3)begin
data_db_char[15][23:16]=data_db[7:0];
data_db_char[14][23:16]=data_db[15:8];
data_db_char[13][23:16]=data_db[23:16];
data_db_char[12][23:16]=data_db[31:24];
data_db_char[11][23:16]=data_db[39:32];
data_db_char[10][23:16]=data_db[47:40];
data_db_char[9][23:16] =data_db[55:48];
data_db_char[8][23:16] =data_db[63:56];
data_db_char[7][23:16] =data_db[71:64];
data_db_char[6][23:16] =data_db[79:72];
data_db_char[5][23:16] =data_db[87:80];
data_db_char[4][23:16] =data_db[95:88];
data_db_char[3][23:16] =data_db[103:96];
data_db_char[2][23:16] =data_db[111:104];
data_db_char[1][23:16] =data_db[119:112];
data_db_char[0][23:16] =data_db[127:120];
end
else if(state_c==S4)begin
data_db_char[15][31:24]=data_db[7:0];
data_db_char[14][31:24]=data_db[15:8];
data_db_char[13][31:24]=data_db[23:16];
data_db_char[12][31:24]=data_db[31:24];
data_db_char[11][31:24]=data_db[39:32];
data_db_char[10][31:24]=data_db[47:40];
data_db_char[9] [31:24]=data_db[55:48];
data_db_char[8] [31:24]=data_db[63:56];
data_db_char[7] [31:24]=data_db[71:64];
data_db_char[6] [31:24]=data_db[79:72];
data_db_char[5] [31:24]=data_db[87:80];
data_db_char[4] [31:24]=data_db[95:88];
data_db_char[3] [31:24]=data_db[103:96];
data_db_char[2] [31:24]=data_db[111:104];
data_db_char[1] [31:24]=data_db[119:112];
data_db_char[0] [31:24]=data_db[127:120];
end
else if(state_c==S5)begin
data_db_char[15][39:32]=data_db[7:0];
data_db_char[14][39:32]=data_db[15:8];
data_db_char[13][39:32]=data_db[23:16];
data_db_char[12][39:32]=data_db[31:24];
data_db_char[11][39:32]=data_db[39:32];
data_db_char[10][39:32]=data_db[47:40];
data_db_char[9] [39:32]=data_db[55:48];
data_db_char[8] [39:32]=data_db[63:56];
data_db_char[7] [39:32]=data_db[71:64];
data_db_char[6] [39:32]=data_db[79:72];
data_db_char[5] [39:32]=data_db[87:80];
data_db_char[4] [39:32]=data_db[95:88];
data_db_char[3] [39:32]=data_db[103:96];
data_db_char[2] [39:32]=data_db[111:104];
data_db_char[1] [39:32]=data_db[119:112];
data_db_char[0] [39:32]=data_db[127:120];
end
else if(state_c==S6)begin
data_db_char[15][47:40]=data_db[7:0];
data_db_char[14][47:40]=data_db[15:8];
data_db_char[13][47:40]=data_db[23:16];
data_db_char[12][47:40]=data_db[31:24];
data_db_char[11][47:40]=data_db[39:32];
data_db_char[10][47:40]=data_db[47:40];
data_db_char[9] [47:40]=data_db[55:48];
data_db_char[8] [47:40]=data_db[63:56];
data_db_char[7] [47:40]=data_db[71:64];
data_db_char[6] [47:40]=data_db[79:72];
data_db_char[5] [47:40]=data_db[87:80];
data_db_char[4] [47:40]=data_db[95:88];
data_db_char[3] [47:40]=data_db[103:96];
data_db_char[2] [47:40]=data_db[111:104];
data_db_char[1] [47:40]=data_db[119:112];
data_db_char[0] [47:40]=data_db[127:120];
end
else if(state_c==S7)begin
data_db_char[15][55:48]=data_db[7:0];
data_db_char[14][55:48]=data_db[15:8];
data_db_char[13][55:48]=data_db[23:16];
data_db_char[12][55:48]=data_db[31:24];
data_db_char[11][55:48]=data_db[39:32];
data_db_char[10][55:48]=data_db[47:40];
data_db_char[9] [55:48]=data_db[55:48];
data_db_char[8] [55:48]=data_db[63:56];
data_db_char[7] [55:48]=data_db[71:64];
data_db_char[6] [55:48]=data_db[79:72];
data_db_char[5] [55:48]=data_db[87:80];
data_db_char[4] [55:48]=data_db[95:88];
data_db_char[3] [55:48]=data_db[103:96];
data_db_char[2] [55:48]=data_db[111:104];
data_db_char[1] [55:48]=data_db[119:112];
data_db_char[0] [55:48]=data_db[127:120];
end
else if(state_c==S8)begin
data_db_char[15][63:56]=data_db[7:0];
data_db_char[14][63:56]=data_db[15:8];
data_db_char[13][63:56]=data_db[23:16];
data_db_char[12][63:56]=data_db[31:24];
data_db_char[11][63:56]=data_db[39:32];
data_db_char[10][63:56]=data_db[47:40];
data_db_char[9] [63:56]=data_db[55:48];
data_db_char[8] [63:56]=data_db[63:56];
data_db_char[7] [63:56]=data_db[71:64];
data_db_char[6] [63:56]=data_db[79:72];
data_db_char[5] [63:56]=data_db[87:80];
data_db_char[4] [63:56]=data_db[95:88];
data_db_char[3] [63:56]=data_db[103:96];
data_db_char[2] [63:56]=data_db[111:104];
data_db_char[1] [63:56]=data_db[119:112];
data_db_char[0] [63:56]=data_db[127:120];
end
else if(state_c==S9)begin
data_db_char[15][71:64]=data_db[7:0];
data_db_char[14][71:64]=data_db[15:8];
data_db_char[13][71:64]=data_db[23:16];
data_db_char[12][71:64]=data_db[31:24];
data_db_char[11][71:64]=data_db[39:32];
data_db_char[10][71:64]=data_db[47:40];
data_db_char[9] [71:64]=data_db[55:48];
data_db_char[8] [71:64]=data_db[63:56];
data_db_char[7] [71:64]=data_db[71:64];
data_db_char[6] [71:64]=data_db[79:72];
data_db_char[5] [71:64]=data_db[87:80];
data_db_char[4] [71:64]=data_db[95:88];
data_db_char[3] [71:64]=data_db[103:96];
data_db_char[2] [71:64]=data_db[111:104];
data_db_char[1] [71:64]=data_db[119:112];
data_db_char[0] [71:64]=data_db[127:120];
end
else if(state_c==S10)begin
data_db_char[15][79:72]=data_db[7:0];
data_db_char[14][79:72]=data_db[15:8];
data_db_char[13][79:72]=data_db[23:16];
data_db_char[12][79:72]=data_db[31:24];
data_db_char[11][79:72]=data_db[39:32];
data_db_char[10][79:72]=data_db[47:40];
data_db_char[9] [79:72]=data_db[55:48];
data_db_char[8] [79:72]=data_db[63:56];
data_db_char[7] [79:72]=data_db[71:64];
data_db_char[6] [79:72]=data_db[79:72];
data_db_char[5] [79:72]=data_db[87:80];
data_db_char[4] [79:72]=data_db[95:88];
data_db_char[3] [79:72]=data_db[103:96];
data_db_char[2] [79:72]=data_db[111:104];
data_db_char[1] [79:72]=data_db[119:112];
data_db_char[0] [79:72]=data_db[127:120];
end
else begin
data_db_char[0] =data_db_char[0] ;
data_db_char[1] =data_db_char[1] ;
data_db_char[2] =data_db_char[2] ;
data_db_char[3] =data_db_char[3] ;
data_db_char[4] =data_db_char[4] ;
data_db_char[5] =data_db_char[5] ;
data_db_char[6] =data_db_char[6] ;
data_db_char[7] =data_db_char[7] ;
data_db_char[8] =data_db_char[8] ;
data_db_char[9] =data_db_char[9] ;
data_db_char[10]=data_db_char[10];
data_db_char[11]=data_db_char[11];
data_db_char[12]=data_db_char[12];
data_db_char[13]=data_db_char[13];
data_db_char[14]=data_db_char[14];
data_db_char[15]=data_db_char[15];
end
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
data_db_chars<=1'b0;
end
else begin
case(data_ab)
0:data_db_chars<=data_db_char[0];
1:data_db_chars<=data_db_char[1];
2:data_db_chars<=data_db_char[2];
3:data_db_chars<=data_db_char[3];
4:data_db_chars<=data_db_char[4];
5:data_db_chars<=data_db_char[5];
6:data_db_chars<=data_db_char[6];
7:data_db_chars<=data_db_char[7];
8:data_db_chars<=data_db_char[8];
9:data_db_chars<=data_db_char[9];
10:data_db_chars<=data_db_char[10];
11:data_db_chars<=data_db_char[11];
12:data_db_chars<=data_db_char[12];
13:data_db_chars<=data_db_char[13];
14:data_db_chars<=data_db_char[14];
15:data_db_chars<=data_db_char[15];
default:data_db_chars<=1'b0;
endcase
end
end
endmodule中文字符识别模块:dat_buf_han.v
module dat_buf_han(clk,rst_n,data_db_chars,data_byte,rxd_finish,rxd_state,data_ab
);
input clk;
input rst_n;
input [7:0]data_byte;
input rxd_finish;
input rxd_state;
input [3:0] data_ab;
output reg [79:0]data_db_chars;
reg [255:0]data_db;
reg char1;
parameter S0 =4'D0 ,
S1 =4'D1 ,
S2 =4'D2 ,
S3 =4'D3 ,
S4 =4'D4 ,
S5 =4'D5 ,
CHECK_S0 =5'D7 ,
CHECK_S1 =5'D8 ,
CHECK_S2 =5'D9 ,
CHECK_S3 =5'D10,
CHECK_S4 =5'D11,
CHECK_S5 =5'D12,
SS1=5'D13,
SS2=5'D14,
SS3=5'D15,
SS4=5'D16,
SS5=5'D17,
CHARS_6 =256'H020002043FE802081FC102027FE200081FC810441FC710441FC4104414440840,//清
CHARS_7 =256'H001000203E40223C222023203EAE2268226822A83EA4012402220C2170280010,//昶
CHARS_8 =256'H000000007FFF0020002000200FE0082008200810081008080808080405020201,//万
CHARS_9 =256'H00103F1021102110217F3F102118213821543F5421122111211021103F102110,//相
CHARS_10=256'H004000807FFE4002204100403FFE00200120011000900088044408221FF11020;//宏
reg finish;
reg finish_0;
reg char;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
finish<=1'b0;
finish_0<=1'b0;
char<=1'b0;
end
else begin
finish_0<=rxd_finish;
finish<=finish_0;
char<=char1;
end
end
reg full_flag;
//状态转换
reg [4:0] state_c_0;
reg [4:0] state_n_0;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
state_c_0<=CHECK_S0;
end
else if(rxd_state==1'b1)begin
state_c_0<=state_c_0;
end
else begin
state_c_0<=state_n_0;
end
end
always@(*)begin
if(rst_n==1'b0)begin
state_n_0=CHECK_S0;
end
else begin
case(state_c_0)
CHECK_S0:if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
else begin
state_n_0=CHECK_S0;
end
CHECK_S1:if(data_byte==8'Hf2)begin
state_n_0=SS1;
end
else if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
CHECK_S2:if(data_byte==8'he0)begin
state_n_0=SS2;
end
else if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
CHECK_S3:if(data_byte==8'hea)begin
state_n_0=SS3;
end
else if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
CHECK_S4:if(data_byte==8'hc6)begin
state_n_0=SS4;
end
else if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
CHECK_S5:if(data_byte==8'he5)begin
state_n_0=SS5;
end
else if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
SS1:if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
else begin
state_n_0=CHECK_S0;
end
SS2:if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
else begin
state_n_0=CHECK_S0;
end
SS3:if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
else begin
state_n_0=CHECK_S0;
end
SS4:if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
else begin
state_n_0=CHECK_S0;
end
SS5:if(data_byte==8'HCD)begin
state_n_0=CHECK_S1;
end
else if(data_byte==8'Hcf)begin
state_n_0=CHECK_S2;
end
else if(data_byte==8'Hba)begin
state_n_0=CHECK_S3;
end
else if(data_byte==8'Hea)begin
state_n_0=CHECK_S4;
end
else if(data_byte==8'Hc7)begin
state_n_0=CHECK_S5;
end
else begin
state_n_0=CHECK_S0;
end
default:state_n_0=CHECK_S0;
endcase
end
end
//中文字符模块
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
data_db=1'b0;
char1=1'b0;
end
else if(finish==1'b0||full_flag==1'b1)begin
data_db=data_db;
char1=1'b0;
end
else if(state_c_0==SS1)begin
data_db=CHARS_8;
char1=1'b1;
end
else if(state_c_0==SS2)begin
data_db=CHARS_9;
char1=1'b1;
end
else if(state_c_0==SS3)begin
data_db=CHARS_10;
char1=1'b1;
end
else if(state_c_0==SS4)begin
data_db=CHARS_7;
char1=1'b1;
end
else if(state_c_0==SS5)begin
data_db=CHARS_6;
char1=1'b1;
end
else begin
data_db=data_db;
char1=1'b0;
end
end
reg [79:0]data_db_char[15:0];
//状态转换
reg [3:0] state_c;
reg [3:0] state_n;
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
state_c<=S0;
end
else begin
state_c<=state_n;
end
end
always@(*)begin
if(rst_n==1'b0)begin
state_n=S0;
end
else begin
case(state_c)
S0:if(char1==1'b1)begin
state_n=S1;
end
else begin
state_n=S0;
end
S1:if(char1==1'b1)begin
state_n=S2;
end
else begin
state_n=S1;
end
S2:if(char1==1'b1)begin
state_n=S3;
end
else begin
state_n=S2;
end
S3:if(char1==1'b1)begin
state_n=S4;
end
else begin
state_n=S3;
end
S4:if(char1==1'b1)begin
state_n=S5;
end
else begin
state_n=S4;
end
S5:state_n=S5;
default:state_n=S0;
endcase
end
end
//输出模块
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
full_flag=1'b0;
end
else if(state_c==S5)begin
full_flag=1'b1;
end
else begin
full_flag=1'b0;
end
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
data_db_char[0] =1'b0;
data_db_char[1] =1'b0;
data_db_char[2] =1'b0;
data_db_char[3] =1'b0;
data_db_char[4] =1'b0;
data_db_char[5] =1'b0;
data_db_char[6] =1'b0;
data_db_char[7] =1'b0;
data_db_char[8] =1'b0;
data_db_char[9] =1'b0;
data_db_char[10]=1'b0;
data_db_char[11]=1'b0;
data_db_char[12]=1'b0;
data_db_char[13]=1'b0;
data_db_char[14]=1'b0;
data_db_char[15]=1'b0;
end
else if(char==1'b0)begin
data_db_char[0] =data_db_char[0] ;
data_db_char[1] =data_db_char[1] ;
data_db_char[2] =data_db_char[2] ;
data_db_char[3] =data_db_char[3] ;
data_db_char[4] =data_db_char[4] ;
data_db_char[5] =data_db_char[5] ;
data_db_char[6] =data_db_char[6] ;
data_db_char[7] =data_db_char[7] ;
data_db_char[8] =data_db_char[8] ;
data_db_char[9] =data_db_char[9] ;
data_db_char[10]=data_db_char[10];
data_db_char[11]=data_db_char[11];
data_db_char[12]=data_db_char[12];
data_db_char[13]=data_db_char[13];
data_db_char[14]=data_db_char[14];
data_db_char[15]=data_db_char[15];
end
else if(state_c==S1)begin
data_db_char[15][15:0]=data_db[15:0];
data_db_char[14][15:0]=data_db[31:16];
data_db_char[13][15:0]=data_db[47:32];
data_db_char[12][15:0]=data_db[63:48];
data_db_char[11][15:0]=data_db[79:64];
data_db_char[10][15:0]=data_db[95:80];
data_db_char[9] [15:0]=data_db[111:96];
data_db_char[8] [15:0]=data_db[127:112];
data_db_char[7] [15:0]=data_db[143:128];
data_db_char[6] [15:0]=data_db[159:144];
data_db_char[5] [15:0]=data_db[175:160];
data_db_char[4] [15:0]=data_db[191:176];
data_db_char[3] [15:0]=data_db[207:192];
data_db_char[2] [15:0]=data_db[223:208];
data_db_char[1] [15:0]=data_db[239:224];
data_db_char[0] [15:0]=data_db[255:240];
end
else if(state_c==S2)begin
data_db_char[15][31:16]=data_db[15:0];
data_db_char[14][31:16]=data_db[31:16];
data_db_char[13][31:16]=data_db[47:32];
data_db_char[12][31:16]=data_db[63:48];
data_db_char[11][31:16]=data_db[79:64];
data_db_char[10][31:16]=data_db[95:80];
data_db_char[9] [31:16]=data_db[111:96];
data_db_char[8] [31:16]=data_db[127:112];
data_db_char[7] [31:16]=data_db[143:128];
data_db_char[6] [31:16]=data_db[159:144];
data_db_char[5] [31:16]=data_db[175:160];
data_db_char[4] [31:16]=data_db[191:176];
data_db_char[3] [31:16]=data_db[207:192];
data_db_char[2] [31:16]=data_db[223:208];
data_db_char[1] [31:16]=data_db[239:224];
data_db_char[0] [31:16]=data_db[255:240];
end
else if(state_c==S3)begin
data_db_char[15][47:32]=data_db[15:0];
data_db_char[14][47:32]=data_db[31:16];
data_db_char[13][47:32]=data_db[47:32];
data_db_char[12][47:32]=data_db[63:48];
data_db_char[11][47:32]=data_db[79:64];
data_db_char[10][47:32]=data_db[95:80];
data_db_char[9] [47:32]=data_db[111:96];
data_db_char[8] [47:32]=data_db[127:112];
data_db_char[7] [47:32]=data_db[143:128];
data_db_char[6] [47:32]=data_db[159:144];
data_db_char[5] [47:32]=data_db[175:160];
data_db_char[4] [47:32]=data_db[191:176];
data_db_char[3] [47:32]=data_db[207:192];
data_db_char[2] [47:32]=data_db[223:208];
data_db_char[1] [47:32]=data_db[239:224];
data_db_char[0] [47:32]=data_db[255:240];
end
else if(state_c==S4)begin
data_db_char[15][63:48]=data_db[15:0];
data_db_char[14][63:48]=data_db[31:16];
data_db_char[13][63:48]=data_db[47:32];
data_db_char[12][63:48]=data_db[63:48];
data_db_char[11][63:48]=data_db[79:64];
data_db_char[10][63:48]=data_db[95:80];
data_db_char[9] [63:48]=data_db[111:96];
data_db_char[8] [63:48]=data_db[127:112];
data_db_char[7] [63:48]=data_db[143:128];
data_db_char[6] [63:48]=data_db[159:144];
data_db_char[5] [63:48]=data_db[175:160];
data_db_char[4] [63:48]=data_db[191:176];
data_db_char[3] [63:48]=data_db[207:192];
data_db_char[2] [63:48]=data_db[223:208];
data_db_char[1] [63:48]=data_db[239:224];
data_db_char[0] [63:48]=data_db[255:240];
end
else if(state_c==S5)begin
data_db_char[15][79:64]=data_db[15:0];
data_db_char[14][79:64]=data_db[31:16];
data_db_char[13][79:64]=data_db[47:32];
data_db_char[12][79:64]=data_db[63:48];
data_db_char[11][79:64]=data_db[79:64];
data_db_char[10][79:64]=data_db[95:80];
data_db_char[9] [79:64]=data_db[111:96];
data_db_char[8] [79:64]=data_db[127:112];
data_db_char[7] [79:64]=data_db[143:128];
data_db_char[6] [79:64]=data_db[159:144];
data_db_char[5] [79:64]=data_db[175:160];
data_db_char[4] [79:64]=data_db[191:176];
data_db_char[3] [79:64]=data_db[207:192];
data_db_char[2] [79:64]=data_db[223:208];
data_db_char[1] [79:64]=data_db[239:224];
data_db_char[0] [79:64]=data_db[255:240];
end
else begin
data_db_char[0] =data_db_char[0] ;
data_db_char[1] =data_db_char[1] ;
data_db_char[2] =data_db_char[2] ;
data_db_char[3] =data_db_char[3] ;
data_db_char[4] =data_db_char[4] ;
data_db_char[5] =data_db_char[5] ;
data_db_char[6] =data_db_char[6] ;
data_db_char[7] =data_db_char[7] ;
data_db_char[8] =data_db_char[8] ;
data_db_char[9] =data_db_char[9] ;
data_db_char[10]=data_db_char[10];
data_db_char[11]=data_db_char[11];
data_db_char[12]=data_db_char[12];
data_db_char[13]=data_db_char[13];
data_db_char[14]=data_db_char[14];
data_db_char[15]=data_db_char[15];
end
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
data_db_chars<=1'b0;
end
else begin
case(data_ab)
0:data_db_chars<=data_db_char[0];
1:data_db_chars<=data_db_char[1];
2:data_db_chars<=data_db_char[2];
3:data_db_chars<=data_db_char[3];
4:data_db_chars<=data_db_char[4];
5:data_db_chars<=data_db_char[5];
6:data_db_chars<=data_db_char[6];
7:data_db_chars<=data_db_char[7];
8:data_db_chars<=data_db_char[8];
9:data_db_chars<=data_db_char[9];
10:data_db_chars<=data_db_char[10];
11:data_db_chars<=data_db_char[11];
12:data_db_chars<=data_db_char[12];
13:data_db_chars<=data_db_char[13];
14:data_db_chars<=data_db_char[14];
15:data_db_chars<=data_db_char[15];
default:data_db_chars<=1'b0;
endcase
end
end
endmodule