Memory barrier |
memory barriers |
It is a set of processor instructions, for implementing a sequential operation limit memory |
Cache line |
Cache line |
The minimum unit of storage that can be allocated in the cache, it will load the entire cache line fill cache line while the processor, a plurality of memory read cycles required |
Atomic operation |
atomic operations |
Or a series of operations can not be interrupted |
A cache line fill |
cache line fill |
When the processor recognizes the number of read operations from the memory is cacheable, the processor reads the entire cache line to the appropriate cache (L1, L2, L3, or all) |
Cache Hit |
cache hit |
If the cache line fill operation of the memory location is still accessible to the processor when the next address. The processor reads the operands from the cache instead of reading from memory |
Write hit |
write hit |
When the processor operand is written back to a memory cache area, it first checks the cache memory address is in the cache line, if there is a valid cache line, the processor will return to write the operand cache instead of writing back to memory, this operation is called write hit |
Write miss |
write misses the cache |
A valid cache line is written to the memory area does not exist |