This article briefly explain GPIO multiplexing, configurable GPIO variety of ways, this article only describes how to configure GPIO IOMUX by the way, is mainly applied to Feiling OKMX6Q-CV1.3 platform Linux4.1.15 operating system, you can also refer to other platforms, but there will be differences between different platforms, customers need to modify to suit their own use.
First, the use IOMUX way configurable GPIO
1. Example UART2_TX pins on the base plate, this pin can be seen that the current function of a serial function, this pin is multiplexed with the GPIO is used, the hardware may be provided by manual Feiling view corresponding to the pin padname is EIM_D26.
2. In the kernel source linux4.1.15 / arch / arm / boot / dts / imx6q-pinfunc.h EIM_D26 search macros can see the following:
among them
#define |
0x0bc 0x3d0 0x000 |
MX6QDL_PAD_EIM_D26__GPIO3_IO26 |
0x5 0x0 |
As for the definition of the GPIO pin
3. linux4.1.15 / arch / arm / boot / dts / imx6qdl-sabresd.dtsi device tree reconfigure the pin, first search to find relevant EIM_D26 pin configuration, you can see the original function is configured to be serial Features:
pinctrl_uart2:uart2grp {
fsl,pins= <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
&uart2{
pinctrl-names= "default";
pinctrl-0= <&pinctrl_uart2>;
status= "okay";
};
The status = "okay" amended as: status = "disabled"
&uart2{
pinctrl-names= "default";
pinctrl-0= <&pinctrl_uart2>;
status= "disabled";
};
Above modifications are off the serial function call, and then subsequently adding configure the GPIO pin function:
After completion of the above modified, recompiled, the new programming and the generated image to the development board.
Pin multiplexing principles are: add functionality to the pin want to achieve in the device tree, and the previous multiplexing features removed, nothing can be added directly to functions.
Operation Second, the file system
The above operation is completed the pin multiplexing kernel configuration, let's look at how applications operate; the development board to start to do the following in the file system.
❶ calculated corresponding values GPIOn_IOx sys / class / gpio a = (n-1) * 32 + x
Then GPIO3_IO26 = (3-1) * 32 + 26 = 90
❷ GPIO3_IO26 to the output.
GPIO pin number echo 90> / sys / class / gpio / export system for notifying the need to export control
The output pin is set ❸
echo out> / sys / class / gpio / gpio90 / direction output to the GPIO
❹ set the level of the output pin
echo 1> / sys / class / gpio / gpio90 / value output is high
echo 0> / sys / class / gpio / gpio90 / value output is low
After setting the high level or a low level, using a multimeter to measure the level value of the specific pin.
❺ cancel export the pin
echo 90> / sys / class / gpio / unexport cancel the export notification system
The pins as inputs ❻
GPIO pin number echo 90> / sys / class / gpio / export system for notifying the need to export control
echo in> / sys / class / gpio / gpio90 / direction input to the GPIO pin high to the case, the input is the high level to the low level and vice versa
View the current value is set to input mode by cat / sys / class / gpio / gpio90 / value command
The above is the entire process of a pin multiplexing function, the following is a brief look at some configuration parameters.
Third, the interpretation of some of the parameters
In the imx6q-pinfunc.h
#define |
0x0bc0x3d0 0x000 0x5 0x0 |
MX6QDL_PAD_EIM_D26__GPIO3_IO26 |
This 5 worth meaning, interpretation has been done
/* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>*/
In imx6qdl-sabresd.dtsi also has a worthy setting:
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x30b0
More than six parameters are the following correspondence relationship:
0x0bc |
0x3d0 |
0x000 |
0x5 |
0x0 |
0x30b0 |
mux_reg_ofs |
conf_reg_ofs |
input_reg_ofs |
mux_mode |
input_val |
pad_ctrl |
These specific values of the parameters are configured according to IOMUX find chapters CPU manual.
Determining a value of 1. mux_reg_ofs
In padname CPU manual search, EIM_D26 EIM_DATA26 pin is in the manual CPU, as shown circled in red block address is the offset value of mux_reg_ofs.
2. Determine the value of conf_reg_ofs
Search EIM_DATA26, if the red circle block shall be the value of the offset address.
3. The determination value is input_reg_ofs
iMX6 Q the CPU without manual corresponding to the pin as an input when gpio configuration, it is 0x000, then the corresponding input_val, this value is also to 0x0.
4. Determine the value of mux_mode
Search IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26, you can see this value is 0x5.
The determination value of pad_ctrl
Search IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, you can see the meaning of the bits of the register, the value is determined according to their actual situation, which does not cut the whole register more digits, please see CPU manual itself.
These are the small series of GPIO multiplexing some simple understanding, I hope for your help. Limited small series level there may be some flaws, please understand. For more in-depth knowledge, if you want to learn you can combine CPU manuals and source code for its own research, what good can give us an insight to share, thank you for reading.
Transfer from Feiling embedded official website, the original link: https://www.forlinx.com/article_view_291.html