Microcomputer principle and interface technology (required for review in Chapter 2)

16 / 32-bit basic register

## Use of Segment Register

Instruction pointer register and flag register

 标志寄存器（FLAGS）:用于存放系统的状态标志和控制标志。

Status flag:

是CPU在执行指令的过程中产生的。有的指令影响状态标志，
有的不影响，还有的指令与当前状态标志有关。
标志寄存器中有6个最常用，每个    占1位。分别介绍如下：

1) SF (sign flag):

它和运算结果的最高位相同。最高位为1，则为1，最高位为0，则为0。

2) ZF (zero flag):

若运算结果为0，则ZF＝1；否则ZF＝0。

3) PF (parity flag):

   若运算结果中“1”的个数为偶数，则PF＝1；否则PF＝0。

4) Carry flag CF (carry flag):

加法时，最高位（字节操作时的D7位，字操作时的D15位）是否有进位产生。
减法时，最高位（字节操作时的D7位，字操作时的D15位）是否有借位产生。

5) Auxiliary carry flag AF (auxiliary flag):

8位二进制加法时，第3位向第4位有进位。
8位二进制减法时，第3位向第4位有借位。

6) Overflow flag OF (overflow flag):

   若运算过程中发生了“溢出”，则OF＝1，否则OF=0。 

Control flag
1) Direction flag DF (direction flag)
2) Interrupt enable flag IF (interrupt enable flag)
3) Trace flag TF (trap flag)
1) Direction flag DF (direction flag)
2) Interrupt enable flag IF (interrupt enable flag) )
3) TF (trap flag)

The 32-bit microprocessor has three working modes:

Real address

The real address mode is the method adopted by the 16-bit microprocessor. 32 microprocessor bits are backward compatible. Logical addresses are the addresses used by programmers when writing programs. In real address mode, the memory cell address is 20 bits

 1） 逻辑地址：
16位的段码和16位的偏移量组合在一起称为逻辑地址，表示方式如下：
		段码：偏移量

2）物理地址：
物理地址＝段首地址＋偏移量＝24×段码＋偏移量

Virtual address method (protection method)

  是最常用的方式，适用于多任务环境，在这种方式下，
  80386才能发挥它自身的     强大功能，所以也称本性方式。
  它的特点是：
 ① 通过逻辑（虚拟）— 线性 — 物理地址的寻找方式来实现存储器的管理，由于   逻辑地址很大，既能实现大程序的运行，又可以方便地实现多任务的分配和管理。
 ② 能实现16位或32位的运算。
 ③ 在保护方式下，可以转入到虚拟8086的方式运行。

Logical address: In the
virtual address mode, the logical address is a segment selection code plus an offset from the specified address in the specified segment , which is expressed as [segment selection code: offset].
Linear address In the
virtual address mode, the segment base address is obtained indirectly by looking up the table. The role of the segment selection code is to select a description item (descriptor) in the segment description table, and the 32-bit segment base address and 20-bit segment limit (given the length of the segment) are given in the description item.

Virtual 8086 mode

Understand three ways of working:

Working mode understanding

The difference between the three modes

8086:

8086 structure:

Logical structure:

Internal structure:

The relationship between EU and BIU:

Summary of EU and BIU:

80386

 32位80386微处理器是为多用户和多任务操作系统而设计的
 具有32位寄存器和数据通道
 支持32位地址和数据类型

80386 logical structure:

Bus interface unit BIU:

The bus interface component is responsible for getting in touch with the outside through the data bus, address bus and control bus, including accessing memory prefetch instructions, reading / writing data and accessing I / O ports to read / write data and other operations and other control functions.

Central processing unit:

Memory management unit MMU:

Logic diagram

Pentium microprocessor

Overview:

Pentium main components:

1. Bus interface components
2. U / V pipeline
3. Code cache and data cache
4. Instruction prefetch unit IPU, instruction decoder IDU, control ROM and branch target buffer BTB
5. Control components
6. Floating point processing unit
7. Segmentation and paging parts

Pentium advanced technology:

1. Advanced structural system

2. Combination of CISC and RISC

3. Superscalar pipeline

4. Advanced branch prediction technology

Pentium logic diagram:

Pentium register set:

Pentium summary

Segment register:

The segment register stores the segment selector

Segment selector

13 + 1 + 2 (bit)
13: description index DI : refers to the sequence number of the descriptor in the descriptor table
1: descriptor indication bit TI: TI = 0-> GDT (global descriptor)
2: ** privileged level PRL : ** TI = 1-> LBI (local descriptor)

Segment descriptor

advantage

1. Expand storage space
2. Implement virtual storage
3. Multitask isolation

Segment register summary

Pentium's main signals and their meaning

Focus on

Address line and control signal

A31 ~ A3: address line
AP: address even check code bit
ADS # address status output signal
A20M # : address line mask signal above A20
APCHK # address verification error signal

Data line and control signal

D63 ~ D0 : data line
BE7 # ~ ​​BE0 : byte enable signal
DP7 ~ DP0 : odd / even parity signal
PCHK : read check
DEN # : odd / even parity enable signal

Bus cycle control signal

D / C : data / control
M / IO : memory and IO
W / R : read / write
LOCK : bus lock
SCYC : split cycle
NA : next address valid signal
BRDY : ready to send signal

Bus arbitration signal

System control signal

The difference between init and reset:

Pentium's bus status and bus cycle:

Overview:

Pentium oneBus cycleUsually consists of multipleClock cycleComposition, and one clock cycle corresponds to oneBus statusSo a bus cycle consists of multiple bus states

Several bus state definitions of Pentium

Transition between bus states:

Pentium's bus status and bus cycle summary

Pentium's interrupt technology

The role of interruption:

1. Task switching
2. IO device works with cpu
3. Real-time signal
4. Check, report, and handle errors in system operation

Classification of interruptions:

Software interrupt
Hardware interrupt

Interrupt vector table

   概述：放置256个中断向量（入口地址）即称 中断向量表  ，每个中断矢量占据4个字节	，地址较高的两个字节放入口地址的段地址，较低两位放置偏移地址

Hardware interruption and its response process

(1) Responding process of maskable interrupt INTR

(2) Responding process of non-maskable interrupt INTR

Interrupt handler structure pattern

Flow chart of 8086 interrupt response process

Summary of Pentium's interrupt technology:

Mind map of this chapter: