MRAM is a non-volatile storage technology that can retain its contents for at least 10 years without the need for power. It is suitable for commercial applications that need to save data during system crashes. MRAM-based devices can provide a solution for "black box" applications because it writes data at the speed of SRAM while retaining data before total power consumption occurs.
MRAM and memory
Comparison of memory options Compared with other memory technology options, MRAM has obvious advantages (Table 1 below).
Table 1 MRAM has comparative advantages compared with other memory technologies
Flash is
a technology that uses charge storage on a piece of floating polysilicon (floating gate) that covers the gate oxide. Programming the flash bit cell requires a high-voltage field that can accelerate the electrons fast enough to overcome the energy barrier of the oxide between the silicon and the floating gate.
This causes electrons to penetrate the oxide and charge the floating gate, thereby changing the threshold voltage of the bit cell transistor. The repeated transfer of electrons through the oxide gradually wears out the oxide material, and the flash memory is limited to 10K-1M write cycles before the bit no longer functions.
Continuous writing will consume some flash memory within 10 days. At the same time, because it does not involve charging or discharging, MRAM can withstand unlimited write cycles. During programming, the magnetic poles are rotated, which is a lossless and lossless operation.
During programming, the flash lamp requires high voltage to pass electrons through the oxide material. MRAM uses a current that generates a magnetic field to program the free layer. In addition, flash memory performs programmer erase operations on large blocks of the memory array. MRAM performs writing on a single address.
SRAM
SRAM uses active transistors that maintain CMOS logic levels and requires power to retain memory content. The content of the MRAM memory is maintained in the polarity of its free magnetic layer. Since this layer is magnetic, it can maintain its state even without power.
As technology continues to shrink the size of SRAM cells, smaller geometric devices tend to leak more current. For a single cell, this leakage is small, but when multiplied by millions of cells in a storage device, the leakage becomes obvious. As technology shrinks, this impact is expected to remain. In view of the non-volatility of MRAM, power-down techniques can be used in the system to achieve zero current leakage.
Battery-powered SRAM
consists of an SRAM unit and a battery packaged in the same package. This non-volatile memory uses battery power to retain memory contents. At the same time, MRAM does not require batteries to save data, and performs read/write operations at a faster speed than battery-backed SRAM. This improves reliability and eliminates environmental issues related to battery handling.
Compared with MRAM, EEPROM has much slower programming speed and limited write cycle capability.
NVSRAM is
also called non-volatile SRAM, which combines SRAM and EEPROM functions. It will store data from SRAM to EEPROM when power is off. But the data transmission is very slow, and a large external capacitor is required to maintain the power of the NVSRAM during the data transmission. MRAM provides a faster write speed, and can write data during normal system operation.
Therefore, minimum data transfer during power failure is necessary. Applications that use MRAM can also benefit from safe writing to memory without the need for large external capacitors.
FRAM
Another non-volatile RAM ferroelectric RAM (FRAM) has a typical small array size, ranging from 4Kbit to 1Mbit. The size of the array is small, because the technology has limited scalability and cannot further reduce the size of the bit cell.
Without this scalability limitation, MRAM can provide a larger memory array. And the programming speed of MRAM is faster than FRAM. Some FRAMs have a limited cycle capacity (for example, 10 billion cycles). They also need to refresh the memory after reading, because this operation will destroy the contents of the bit cell being read.
DRAM
uses this technology, and the memory must be refreshed frequently to retain data.