Some errors in quartus using Verilog

error

1. Error (10663): Verilog HDL Port Connection error at floatMulit32.v(16): output or inout port “sign” must be connected to a structural net expression . The parameter type is incorrect when it is instantiated. Change
   the reg type to wire
2. Error (12007): Top-level design entity “floatMulit32” is undefined
   This is the name of your outermost module, which must be the same as your project name