LVDS (Low-Voltage Differential Signaling ) is a signal transmission mode level standard proposed by National Semiconductor (NS, now TI) in 1994. It uses extremely low voltage swing and high speed Differential transmission of data can realize point-to-point or point-to-multipoint connection. It has the advantages of low power consumption, low bit error rate, low crosstalk, and low radiation. It has been widely used in serial high-speed data communications.
The LVDS technical specification has two standards, namely the ANSI/TIA/EIA-644 standard of TIA (Telecommunications Industry Alliance)/EIA (Electronic Industry Alliance) (LVDS interface is also called RS-644 interface) and IEEE 1596.3 standard.
The LVDS level standard uses a pair (two) of differential signal lines to transmit data. Our most common differential signal line is USB (Universal Serial Bus ) . Nowadays, any PC computer has a USB interface, which can be used to connect U disk, keyboard, mouse, printer, mobile hard disk Wait, as shown below:
HDMI (High Definition Multimedia Interface ) is a digital audio and video interface technology, a dedicated digital interface suitable for image transmission, which consists of 4 pairs of differential lines. The SATA (Serial Advanced Technology Attachment, Serial ATA Interface Specification) hard disk we use also contains two pairs of differential signal lines for receiving and sending, as shown in the following figure:
Readers with DDR3 SDRAM application experience will also find several pairs of differential lines, as shown in the following figure:
I’m sorry to tell you that the differential signal lines of the above interfaces are not strictly LVDS level standards (but many basic concepts are connected). In other words, not all differential signal lines are LVDS level. Standards , there are many specific levels of data transmission using differential signal lines, LVDS is just one of them.
For example, HDMI using the TMDS (the Minimized Differential Signal Time, minimized differential signaling) , the use of DDR3 SSTL (the Stub Series Logic terminated, stub series termination logic ). The level standards used by HDMI (TMDS), USB and SATA are very similar to LVDS, but from their specifications, they are not standard LVDS (they are also "low voltage differential signals", but not the LVDS we are talking about here). Think of it as the same level standard (just like we can’t think that the 5V TTL level standard is the same as the 5V CMOS level standard, although it seems that the parameters are not very different), and SSTL (including SSTL_3, SSTL_2, SSTL_18, SSTL_15) and LVDS is not a thing at all.
Of course, as long as they use differential signal lines for data transmission applications, their requirements for PCB wiring are similar. We will detail this in the "High-speed PCB Design" column.
Despite this (the above are not LVDS level standards), the application of LVDS level standard interfaces is still very wide, and the LCD display with LVDS interface is one of them, which is the general interface standard of LCD Panel. So what makes LVDS so popular? Let's start with the most basic LVDS hardware transceiver.
Usually most low-speed digital logic levels (such as TTL, CMOS) are judged high or low based on the amplitude of the voltage to the reference ground, as shown in the following figure:
LVDS is completely different. It judges the high and low level by the relative magnitude of the voltage between the non-inverting terminal and the inverting terminal of the data receiver , rather than the common ground (GND) through the non-inverting or inverting terminal.
The basic structure of LVDS transmitter and receiver is shown in the figure below. It uses two wires (ie differential signal wires) to transmit a signal, and uses a constant current source ( Current Source ) to drive, that is, current drive type (while TTL, CMOS and other level standards are voltage drive type).
Among them, the field effect transistors Q1, Q2, Q3, and Q4 (not necessarily field effect transistors ) in the driver ( Driver ) , because the LVDS technical specifications mainly focus on the electrical, interconnection and line termination of the LVDS interface. For the production process, There is no clear requirement for transmission medium and power supply voltage, that is to say, it can be realized by CMOS, GaAs or other processes. Black cats and white cats that can catch mice are good cats) to form a full-bridge switch circuit to control 3.5mA constant a current flow direction of the source, the receiver ( receiver ) connected in parallel between the inverting terminal of the same phase and a 100 ohm termination resistor, so that the current through the resistor to produce a voltage, and then after the receiver is determined on the formation of high and low .
When Q2 and Q3 are turned on and Q1 and Q4 are turned off, the constant current source current flows to the receiver through Q3, passes through the 100 ohm termination resistor and returns to the drive end, and finally to the ground (GND) via Q2, 3.5mA The current in the 100 ohm resistor produces a 350mV voltage drop. At this time, the non-inverting terminal voltage is higher than the inverting terminal voltage, and the output is high level "H", as shown in the following figure:
When Q2 and Q3 are turned off and Q1 and Q4 are turned on, the constant current source current flows to the receiver through Q1 to the right, and goes up through the 100 ohm termination resistor and returns to the drive end, and finally to ground (GND) through Q4. The 3.5mA current also produces a 350mV voltage drop across the 100 ohm resistor, but at this time the non-inverting terminal voltage is lower than the inverting terminal voltage, and the output is high level "L", as shown in the following figure:
Usually we simplify the LVDS receiver and transmitter to something like the following figure:
As shown in the figure below (from TI's LVDS transceiver chip SN65LVDS180 data manual)
It can be seen from the principle of LVDS structure that a pair of differential signal lines can only carry out data transmission in one direction, that is, simplex communication (also known as point-to-point transmission), but our common USB interface only uses one For differential signal lines, why can it be transmitted in both directions? The reason is simple, it is a combination of two pairs of drivers and receivers, as shown in the figure below:
This is a half duplex ( half duplex ) configuration structure, that is to say, the differential signal line can still only transmit data in one direction at any time, but it can perform two-way data transmission in a time-sharing manner. When the driver 1 to the receiver 1. When sending data, driver 2 and receiver 2 are equivalent to invalid, and vice versa.
Of course, the actual structure of the USB bus is much more complicated, as shown in the figure below (from the USB2.0 specification, far away)
Let's take a look at the electrical parameters of the LVDS driver as shown in the figure below (from TI's LVDS transceiver chip SN65LVDS180 data manual)
In the table above the VOD (Differential Output Voltage Magnitude ) that is the differential output voltage amplitude of the driver , i.e. 350mV voltage drop is generated in the termination resistor, we can use the figure (note: a differential mode signal):
There is also a Voc(ss) (Steady-state common-mode output voltage ) in the table, that is, what is the steady -state common-mode output voltage ? I don't quite understand! Let's find Figure 3 in the data manual according to the diagram, as shown in the following figure:
Oh, it turned out to be the average value of the converted LVDS signal voltage to the common ground when the driver inputs a digital signal (before it is converted into an LVDS signal), also called Vos ( Offset Voltage ). Other TI data manuals use VOS As shown in the figure below: (from TI's LVDS transceiver chip model SN65LVDS049 data manual)
As we said before, when the LVDS level standard is used to transmit high and low levels, the voltage drop of +350mV or -350mV received at the receiving end is only a differential mode signal, in fact there is a certain common mode signal, which does not affect the receiver's data Judgment.
When the driver sends a high level "H" to the receiver, the equivalent diagram is as follows (note: this equivalent diagram is only suitable for very short transmission lines):
When the driver sends a low level "L" to the receiver, its equivalent diagram is shown in the figure below
Combining the above two equivalent circuits, we have the level waveform diagram as shown in the figure below:
In other words, when the LVDS is switching between high and low levels, the current of the current source at the moment of commutation, the current flowing through the termination resistor is zero, so the voltage across the termination resistor is Vos (the voltage across the resistor is the same, so there is no voltage Drop, there is no current), as shown in the figure below:
Of course, this current commutation conversion moment is very short, usually only a few hundred picoseconds, as shown in the following figure:
The input electrical parameters of the receiver are shown in the figure below:
Therefore, we can also use the following figure to show the noise tolerance of the LVDS level standard (for noise tolerance, please refer to "Logic Gate 2")
As can be seen from the figure, the noise tolerance of the LVDS level standard is about 1.075V (generally considered its noise tolerance is 1V). Here we just draw the level standard diagram according to the TI data manual without any modification. Different manufacturers The information may be slightly different.
Director, I haven't mentioned why the LVDS signal is fast and has strong anti-interference ability after talking for a long time. Why do some differential lines have capacitors in series? Why is the impedance of different differential lines different? Knowing these basic knowledge, we will discuss these characteristics of the LVDS level standard in the next section.