Verilog learning (7) scan chain of actual combat

One: Introduction to Design for Laterality (DFT)

1: What is testability?

　　It is equivalent to adding a breakpoint to the program segment in debug.

　　The design tool automatically inserts scans into the design, which are inserted into the design later in the design phase after the design has passed simulation. The purpose of the scan is to observe the internal changes of a design or an entire chip in the future.

2：JTAG

　　Scanning is controlled by a special set of test ports called JTAG.

Two: Simple scan example

　　We add scan chain in actual combat 1

1: Add JTAG test port in Intro_Top, add 5 1-bit ports, do not connect them first, these 5 ports are: ScanMode, ScanIn, ScanOut, ScanClr, ScanClk

2: Insert D flip-flops in every I/O path in Intro_Top (top-level design), except for JTAG I/O

　　

3: Add drivers to ScanClk and ScanClr in the testbench, that is, assign values

The above can simply implement the scan chain, and also simply presents the general situation of the scan chain. The following is the extension

4: Add a multiplexer to remove all synchronization behavior, two multiplexers are added to one ff register