8.1 Sequence and properties of multiple clocks
There are hardly any designs that only work on a single clock domain. So far we have seen properties that belong to a single clock. But what if you need to check for time-domain conditions that cross clock boundaries? The so-called CDC (Clock Domain Crossing) problem can be solved with multiple clock assertions.
We'll overhaul how properties/sequences cross clock boundaries. What is the relationship between these two clocks? How is the sampling edge evaluated once the clock domain is crossed? Note that in a single clock system, the sampling edge is always one, the rising or falling edge of the clock. Since there are two (or more) clocks in a multi-clock system, we need to understand how the sampling edge crosses the boundary from one clock to the other. I think it's best to fully understand the basics before writing the actual application.
Note that there is a difference in how Sequence behaves with multiple clocks and how properties behave with multiple clocks. continue reading...
Figure 8.1 shows a simple multi-clock sequence. It says that at (posedge clk0) A is true and the next closest strict (posedge clk1) B is true. Note the "very close next". This is because when you connect two subsequences, each runs on a different clock, and thus can only transition from one clock domain to the next available sampling edge of the next clock domain. This will be clearer when we go into a little more detail.
Jumping forward a bit, this "very close to the next closest edge" semantics is why we use ##1 to cross a clock boundary. So, can you use ##2 when crossing a clock boundary? Keep this question in mind as you learn the basics of multiclock sequences and properties.
Figure 8.1 Multiple Clock Sequence - Basics
8.1.1 Multiple Clock Sequences
The timing diagram in Figure 8.1 shows that 'A' is true when (posedge clk0). The clocks are out of phase, so the next clock edge of clk1 is half a clock delayed from posedge clk0. After posedge clk1 'B' is sampled true, the sequence 'mcloks' will pass. The point here is that ##1@(posedge clk1) is only equal to 1/2 clk1 and not a full cycle, because the next closest strict posedge clk1 arrives in 1/2 a clock cycle. The next clock can occur at any time after clock 0 and will be the 'very close next' edge of the sampled edge of the subsequence.
IMPORTANT: The requirement of ##1 between two subsequences has been removed from 1800_2009 , I leave it here for those who are using 1800-2005 and haven't moved to 1800-2009.
So what happens if clk0 and clk1 are in phase? See Figure 8.2 below. explained in the figure. It goes without saying that the sequence will wait a full clock before sampling 'B'. But it is more important to note that if the clocks on the clock crossing boundary are the same (in phase and in the same period), then the following is true:
@ (posedge clk0) A ##1 @ (posedge clk1) B; is identical to @ (posedge clk0) A ##1 @ (posedge clk0) B; is identical to @ (posedge clk0) A ##1 B;
To reiterate the previous concept, the above is the same because ##1@(posedge xxx ) does not mean 2 clock edges. It just means the next edge of the next clk.
Figure 8.2 Multiple Clock Sequence - Same Clock
8.1.2 Multiple Clock Sequences: Legal and Illegal Sequences
Before we get into the multi-clock properties and based on our observations, let's quickly examine what is legal and illegal for multi-clock sequences. Again, these cases only apply to sequences and not properties.
Bottom line, you can only have ##1 between two subsequences with different clocks. If the clocks on both sides are the same, then there is no such restriction. Figure 8.3 makes it clear.
Figure 8.3 Multiple Clock Sequence - Illegal Condition - 1800-2005 only. Restrictions lifted from 1800-2009
Note to reiterate that the above restrictions apply only to the IEEE 1800-2005 standard. From 1800 to 2009 this restriction has been removed. If you're on 1800-2005 and haven't moved to 1800-2009, I'm still describing the limitations here.
8.1.3 Properties of multiple clocks - 'and' operator
The concept of 'and' of two sequences has been discussed before. But what if the clocks in the sequence are different? An important point to note above is the very next strict notion of subsequent edges. In Figure 8.4, 'a' is sampled high at the posedge of clk0. This triggers an 'and' that results in 'b' and 'c'. Note that 'b' is expected to be true at the next edge of clk1 (after the posedge of clk0). In other words, even if there is a non-overlapping operator in the attribute, we won't wait 1 clock. We just wait for the next posedge of clk1 to check if 'b' is true. The same story applies to 'c'. As shown in Figure 8.4, the property passes if both 'b' and 'c' are present. Like the 'and' of a single clock, the assertion passes after a match of the longest (so to speak) sequence 'c'.
Figure 8.4 Multi-clock properties - 'and' operator between two different clocks
Figure 8.5 shows another scenario that consolidates the 'and' concept of multi-clock assertions. 'And' is between two subsequences using the same clock. This behavior is obvious, but interesting. This is because (@(posedge clk1)b and @(posedge clk1)c) basically acts like '@(posedge clk1)b and c'. Therefore, both 'b' and 'c' must now appear at the next boundary of clk1.
In conclusion, as we have seen before, '@(posedge clk1)b and @(posedge clk1)c' are the same as '@(posedge clk1)b and c'.
Figure 8.5 Multiple Clock Properties - 'And' Operator Between Same Clocks
8.1.4 Properties of multiple clocks - 'or' operator
All the rules for 'and' apply to 'or' - except in the properties of a single clock - when either sequence (i.e. LHS or RHS of the operator) passes the assertion. The concept of 'next strictly subsequent clock edge' is the same as 'and'.
Please refer to Figure 8.6 to better understand the 'or' of a multi-clock sequence. The property passes when @(posedge clk1)b or @(posedge clk2)c occurs. In other words, if @(posedge clk2)c comes before @(posedge clk1)b, the property will pass at @(posedge clk2)c.
Figure 8.6 Multiple Clock Properties - 'Or' Operator
8.1.5 Properties of multiple clocks - 'not' operator
'not' is an interesting operator when it comes to multi-clock assertions.
The assertion in Figure 8.7 works as follows. At posedge clk0, 'a' is true and it triggers subsequent mclocks. The attribute mclocks specifies that @posedge clk1 'b' must be true and 'c' should not be true @posedge clk2. The timing diagram shows that 'a' is true at posedge clk0. On the trailing edge of clk1, 'b' should be true, and because it is, the attribute moves. Since 'and' it looks for 'c' at the next (in other words, posedge clk2 after the first one after the boundary of clk0) is the edge of clk2. Well, 'c' does, but since we have 'not' in front of @(posedgeclk2), the property will fail. The concept of 'not' is the same as that of the properties of a single clock, except that the edges of the clock are evaluated. Simulation logs illustrate this concept.
Figure 8.7 Multiple Clock Properties - 'not' Operator
8.1.6 Multi-Clock Properties - Clock Resolution
Figure 8.8 Multi-Clock Properties - Clock Resolution
These rules are important when dealing with multi-clock properties. The important rule is the illegal rule. The overlap operator cannot be used when the clocks of the preceding and following expressions are different. For different clocks, you must use a non-overlapping implication operator (Figure 8.8).
Figures 8.9 and 8.10 illustrate other important concepts. How does the clock apply (or flow) from one part of the sequence to another? The description in the figure explains how this works.
- In Figure 8.9, the attribute 'mclocks' (posedge clk0) applies to 'A' as well as 'B' because 'B' has no explicit clock. So far so good.
- Then (posedgeclk1) works for 'C'. This also makes sense.
- However, since 'D' does not explicitly specify its own clock, what clock is applied in 'D'?
- According to 1800-2005LRM, 'D' will inherit (posedge clk0) instead of (posedge clk1). This is not very intuitive. But the LRM makes it very clear that the scope of the clock event does not flow out of the enclosing parentheses.
- In our case "'B'##1@(posedge clk1)C" is in brackets. So once we leave the parentheses (posedge clk1) will not flow forward, but (posedge clk0) will advance to the subsequent 'D'.
Figure 8.9 Multi-Clock Properties - Clock Resolution - II
Similarly, the bottom example in Figure 8.9 shows how the clocks "flow" when we have multiple subsequences, each with its own clock. Note that there are three different clocks in this sequence. (posedge clk) flow through 'a'. Then 's1' and 's2' use their own clocks as sampling edges (clocks) for their sequences. But once out of 's2', (posedge clk) is applied to 'f' instead of 's2''s (posedge clk1).
Figure 8.10 Multiple Clock Properties - Clock Resolution - III
Figure 8.10 shows another interesting property. What happens if you need to transition from one clock to another before checking the expression/sequence? Well, you can't do that. In Figure 8.10, we show that (posedge clk1) is immediately followed by (posedge clk0). This does not mean that the property will first wait for (posedge clk1), then wait for (posedge clk0), then apply (posedge clk0) to 'a'. It will simply overwrite (posedge clk1) with (posedge clk0) and apply (posedge clk0) directly to 'a'. This is shown in the equivalent properties at the bottom of the figure.
8.1.7 Multiple Clock Properties - Legal and Illegal Conditions
Figure 8.11 Multiple Clock Properties - Legal and Illegal Conditions
Figure 8.11 is a simple reference to the legal and illegal semantics of the multiclock attribute.
The top example shows that it is possible to have different clocks between the left-hand and right-hand expressions (|=>) as long as the implication operators do not overlap.
The second example shows that this would be illegal if the clocks on both sides of the implication operator were different and the implication operator was an overlapping implication operator (|->).
But as shown in the third example, overlapping operators are perfectly legal if the clocks on both sides of the overlapping operator are the same.
The last example is pretty intuitive because => is equivalent to | -> ##1. Therefore, you can have different clocks on each side of the overlapping operator.