The key to the entire system design lies in the processing of 8K video signals. Up to now, because the 8K standard is not very clear, the corresponding video processing chip manufacturers are also watching, so there are very few related 8K video processing chips. For example, manufacturers such as SiI9779 and SiI9630 currently advertise support for 8K, but they have not launched this function in the end. At present, the main push of 8K technology is Japan's NHK, which is expected to conduct 8K live broadcasts at the 2020 Tokyo Olympics. Fujitsu Co., Ltd. and Matsushita Electric Industrial Co., Ltd. merged the system LSI businesses of the two companies to form Socionext. The new brand reflects the company's core business lies in SoC and competitive Imaging (video and imaging field) and OpticalTransport Network (optical fiber communication network field) technical significance. Socionext launched a single-chip 8K processing chip SCH801A in 2016. SCH801A is consistent with the first part of ARIB STD-B32 encoding standard for Japanese ultra-high-definition satellite broadcasting HEVC. It can decode 8K 60P on a single chip and one channel. It is equipped with a PCI Express second-generation slot and 4 HDMI 2.0 Tx external interfaces. After the 8K video stream is decoded by the front-end chip SCH801A, 4 channels of HMDI2.0 video signals are output. In terms of bandwidth, the maximum bandwidth of HDMI 2.0 is as high as 18Gbps, and the combined bandwidth of the four channels can reach 72Gbps, which is enough to transmit one 8K video signal.
In this design, high-speed FPGA is used to decode the HDMI2.0 signal, and the standard HDMI signal is converted into parallel data data through the HDMI decoding module. The specific HDMI decoding module design block diagram is shown in Figure 3. The TMDS data enters the Deskew module for data realignment and rearrangement; the data enters the TMDS decoder module, and the video data and AUX data are separated from the module. The video data enters the video sampling module and separates clk, HS, VS and video data. The auxiliary data enters the Auxiliary Packet Capture module, and separates control data packets and audio data. After the video data is separated, in order to facilitate data transmission in the wall-splicing processor, when passing through the parallel-serial conversion module of the FPGA, it is converted to serial data for transmission. Each pair of HDMI signals is transmitted through 2 pairs of high-speed serdes signals, which is convenient for the video scheduling module to schedule.
Video scheduling module
In this module, mainly video signal scheduling, clock processing module, communication module, CPU system module, etc. are the core of business control of each module. The video signal cross-scheduling module adopts the high-speed serial space division switching technology to schedule the high-speed serial data signal and transmit the high-speed serial data signal. According to the predetermined correspondence between the input port and the output port, each input high-speed serial data signal is output through the corresponding port and transmitted to the corresponding video processing module.
The clock processing module is used to generate a reference clock signal, and provide the generated reference clock signal to each 8K video module, each video signal processing module, a signal expansion switching platform, and the like. The 8K video module, video signal processing module, and signal expansion switching platform, etc., are synchronized with the system reference clock provided by the single board to generate the module clocks required for the high-speed serial processing business of this module.
Video processing module
The video signal processing module performs deserialization, cutting, scaling, stacking and other processing on the high-speed serial signal after the scheduling of the video signal, and finally outputs the processed image signal.
Through the serialization processing of the signal by the image signal acquisition module and the scheduling of the main control cross module, any required input signal can be obtained at the input port of the video signal processing module. The input signal is a high-speed serial signal and must be deserialized Only after the signal can be processed. Deserialization is the reverse process of serialization. The resolution of the input signal and the size of the window to be displayed are usually different. The image restored from the deserialization module must be scaled. At the same time, the displayed window may span multiple display units, and each unit only Display a part, intercept the required image data by cutting, and perform corresponding scaling processing. Finally, the superimposed image signal is converted into standard 16-channel DVI signal output by the output driving part.
Video Basic Algorithm
