An exploration of RAM usage in FPGAs. Taking 4bitX4 as an example, the data bit width is 4 and the depth is 4.
The first way is to directly call the 4bitX4 RAM. Write control logic to align for reads and writes.
Compilation under quartus ii, resource consumption.
Clock frequency under 85C model.
Clock frequency under 0C model.
The second way is to call 1bitX4 RAM and instantiate it 4 times. Write control logic to align for reads and writes.
Compilation under quartus ii, resource consumption.
Clock frequency under 85C model.
Clock frequency under 0C model.
Judging from the above two situations, the final usage resources of the two RAM usage methods are relatively close, and the second solution is slightly more. From the comprehensive results of the timing model, the clock frequency of the second solution is obviously higher than that of the first solution. In the case of high speed, it is recommended to use option two. Also in the case of a wide bit width, it is convenient to use the generating block statement to reduce the number of instantiations of the same module at the top level.
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Author: Hangzhou Qingcui Technology ALIFPGA
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