FPGA image processing line buffer ( linebuffer ) design one
Author: OpenS_Lee
1 Background knowledge
In FPGA digital image processing, the use of line cache is very frequent. For example, when we need image matrix operations, we need to cache. For example, image mean filtering, median filtering, Gaussian filtering, and sobel edge search all require line cache design. The importance here is not repeated here.
2 FPGA implementation
Figure 1 Row cache daisy-chain structure
As shown in Figure 1 , if we want to design n lines to output at the same time, we connect n lines in series. The size setting of Line_buffer is determined by the size of the image display line (image width). For example 480*272 ( 480 ).
2.1 Design an Intel shift register
Design source code:
Line3 IP settings :
图2 shift register IP
Figure 3 Parameter settings
As shown in Figures 2 and 3 , we need to design 3x3 matrix data, and the data parameters of three rows must be set as shown in Figure 3 at the same time .
Simulation top level:
Simulation results:
Figure 4 Overall effect
Figure 5 One row of data
Figure 6 Two lines of data
Figure 7 Three lines of data
As shown in Figure 7 , when all three rows of data come out, our data are all aligned, indicating that the design is correct.
2.2 Design two xilinx shift register
Source code:
IP settings:
Figure 8 IP setting parameters
Figure 9 Hierarchy
Simulation top level:
Simulation results:
Figure 10 Simulation overall effect
Figure 11 Three lines of data are simultaneously aligned and output
So far, we have completed the IP design line cache of xilinx and altera , but this method is not flexible enough in some cases, so we will introduce the fifo design line cache in the next section.
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