This article is reproduced from: https://blog.csdn.net/a8082649/article/details/24252093
The bin file has been compiled, now study the makefile and record the problems encountered:
1. What does $(@:_config=) mean?
Find the following explanation online
The replacement reference rule in Makefile is used here, similar to the commonly seen example obj=$(srcfiles:%.c=%.o): The corresponding .o file is obtained from .c.
Here is the same reason:
$(@:_config=)
@ represents target smdk2410_config, then $(@:_config=) is to replace _config in smdk2410_config with empty! Get smdk2410; you can print it out with echo Just look at it!
smdk2410_config : unconfig
@echo $(@:_config=) # Print it out
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
But one thing I don't understand is that @ stands for target? The impression seems to be that $@ represents the goal, so I did a test"
all:
@echo $@ output is all
@echo @ output is @
@echo $(@) output is all
So I think the symbol @ is the same as $@ in $()
2. Goal: Dependency
Order
Can a command be directly a filename?
A test has been done to prove that:
Create a makecfg outside and enter echo i am here!
in makefile
all：
@(path/makecfg)
Enter the command make all
It will output i am here!