Verilog module instantiation with parameters

Similar to VHDL's Generic statement, Verilog can also pass parameters during instantiation.

See http://sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html#8.0%20Module%20Instances

The parameters passed are parameters defined in submodules.

The method of passing:
1. module_name #( parameter1, parameter2) inst_name( port_map);

2. module_name #( .parameter_name(para_value), .parameter_name(para_value)) inst_name (port map);

using the # method is similar to port map writing

3.
defparam defparam heirarchy_path.parameter_name = value;
This method is separate from instantiation, and the parameter needs to be specified by writing an absolute path.

Parameter constants are often used to define delay time and variable width. When a module and instance are referenced, parameters defined in the referenced module or instance can be changed by passing parameters. The method of parameter passing is as follows: first define an instance of Adder_16 (sum, a, b), then define two parameter constants time_delay and time_count, and then when calling in the top-level module, you can pass parameters to change the value of the parameter constants , so as to call submodules more flexibly.

• module adder_16(sum,a,b);
•   parameter time_delay=5,time_count=10;
•             ......
• endmodule
• module top;
•   wire[2:0] a1,b1;
•   wire[3:0] a2,b2,sum1;
•   wire[4:0] sum2;
•   adder_16  #(4,8)  AD1(sum1,a1,b1);//time_delay=4,time_count=8
•   adder_16  #(12)   AD2(sum2,a2,b2);//time_delay=12,time_count=10
• endmodule