Understanding of make and Makefile

1. A simple understanding of make and Makefile
   make is a command, and Makefile is a file. The relationship between the two is: the make command is implemented through the Makefile file. In Makefile, it tells the command make how to compile , How to link files.

I heard that as long as the makefile is well written, in the project, the compilation and linking process of many, many files only needs to be done through a make command...

1. Basic rules of makefile
   Object file (object file list): The dependency files required to generate the object file...
   [Command]
   [Command]
   ………………
   The target file is the executable file to be generated.
   Dependency files are the files needed to generate this executable.
   Commands are some commands on the terminal (commands that make needs to execute).
   Note: the command must be preceded by the Tab key

2. Dependency
   means that there are multiple or one of our target files to generate, and the generation rule is defined in the following command, that is to say, if at least one of the following dependency files is larger than the target file. Also new, the following command will be executed.
   I heard that this make rule is the core content of the makefile

3. The working steps of make The
   make command will find the makefile file under the current file, then find the target file in the makefile file, generate the .o file after finding the target file, and finally use the .o file to generate the executable file.
   If the object file is not found, or the following .o dependency file is newer than the object file, the following command will be executed to generate the object file.
   If the following .o file cannot be found, then make will find the dependency file with .o as the target file in the current directory. If it is found, the .o file will be generated according to the rules of using .o as the directory file, and then the current one will be generated. Target file.
   The premise of the above is that both the H file and the C file exist.
   It feels that make finds dependencies layer by layer, and finally generates target files, which finally become executable files. So it's like a chain, only when make is in the process of searching, and one cannot find or is interrupted and an error occurs, make will not continue to execute, and it will jump out and report an error directly. Although the dependency of the target file is found, as long as the file after the colon keeps looking down and cannot be generated, make will no longer proceed, and an error will be reported directly.

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The above is the basic understanding of make and makefile...