Getting Started with FPGAs - Signal Types

signal type

Data types mainly include two types, net type (net tye) and register type (reg type), and only these two types of signals are used in engineering design

Signal width

While defining the signal type, the bit width of the signal must be defined. The default signal bit width is one bit (if we do not define the signal bit width, that is, there is no description, then it is one bit)

The signal bit width depends on the maximum value represented by the signal to be changed, and the unsigned maximum value that the signal can represent: $ 2^n-1 $, where n represents the bit width of the signal

Example:

wire a;		//表示位宽为 1 的信号类型
wire [7:0] a;	//表示位宽为 8 的信号类型

Wire mesh type wire

The wire network type is used to model the physical connection between structured devices. Since the current network type represents the physical connection wire, it does not store logical values and must be driven by the device. Usually assigned with assign

The wire type definition syntax is as follows:

wire [msb: lsb] wire1, wire2 , …… , wiren

msb and lsb define the range and represent the bit width, which must be a constant value. For example, [7:0] is 8-bit bit width, which can be expressed as 8'b0 to 8'b1111_1111
If no range is defined, the default is 1
If no signal type is defined, the default is wire type
Arrays are defined in descending order, for example: [7:0], do not write as [0:7]

register type reg

reg is the most commonly used register type. The register type is usually used to describe the storage unit. The characteristic of the register type signal is that a value is assigned under a certain trigger mechanism, and the original value is retained before the arrival of the next trigger mechanism, but it must be noted Yes: the variable of type reg is not necessarily a storage unit, as described in the always statement, it must be a variable of type reg

The reg type is defined as follows:

reg [msb: lsb] reg1, reg2, …… , regn

msb and lsb define the range and represent the bit width, which must be a constant value. For example, [7:0] is 8-bit bit width, which can be expressed as 8'b0 to 8'b1111_1111
If no range is defined, the default is 1
If the signal type is not defined, the default is wire type, not reg type
Arrays are defined in descending order, for example: [7:0], do not write as [0:7]

Compare wire and reg

From the point of view of simulation analysis

wire corresponds to continuous assignment, such as assign

reg corresponds to process assignment, such as always, initial

wire 型数据常用来表示以 assign 关键字指定的组合逻辑信号，模块的输入输出端口类型都默认为 wire 型，wire 相当于物理连线，默认初始值是 z，reg 型数据表示寄存器模型，用于 always 块、initial 语句中被赋值的变量
wire 使用在连续赋值语句中，reg 用在过程赋值语句(always、initial)中
wire 若无驱动器连接其值为z，reg 默认初始值为不定值 x
wire 表示直通，即输入有变化，输出马上无条件地反映(如与、非门的简单连接)，reg 表示一定要有触发，输出才会反映输入的状态
wire 一般用在组合逻辑中，reg 一般用在时序逻辑中
reg 变量在 always 中有两种情况：

always @(a or b or c)形式的，即不带时钟边沿的，综合出来还是组合逻辑；
always @(posedge clk)形式的，即带有边沿的，综合出来一般是时序逻辑，会包含触发器(Flip-Flop)

always 块不止能实现时序逻辑，还能实现组合逻辑：

如果这个条件是时钟上升沿或下降沿，那硬件模型就是一个触发器，只有是指定了 always@(posedge or negedge)才是触发器
如果这个条件是某一信号的高低电平，那这个硬件模型就是一个锁存器
如果这个条件是赋值语句右侧任意操作数的变化，那这个硬件模型就是一个组合逻辑

对组合逻辑输出变量，可以直接用 assign。即如果不指定为 reg 类型，那么就默认为 1 位 wire 类型，故无需指定 1 位 wire 类型的变量。当然专门指定出 wire 类型，可能是多位或为使程序易读
reg 型数据保持最后一次的赋值，而 wire 型数据需要持续的驱动

在连续赋值语句 assign 中，表达式右侧的计算结果可以立即更新到表达式的左侧，可以理解为逻辑之后直接连接了一条线，这个逻辑对应于表达式的右侧，这条线对应于 wire

在过程赋值语句中，表达式右侧的计算结果在某种条件的触发下放到一个变量当中，这个变量可以声明成 reg 型

reg和wire类似于C、C++的变量，但若此变量要放在begin...end之内，则该变量只能是reg型；在begin...end之外，则用wire型

什么时候使用 reg 或 wire ？

assign 语句中变量需要定义成 wire 型，使用 wire 必须搭配 assign
元件例化时候的输出必须用 wire
input、output 和 inout 的预设值都是 wire
变量放在 begin……end 之内必须使用 reg 变量
在 initial 语句中使用

reg 类型信号并不一定生成寄存器，针对什么时候用 wire 类型，什么时候用 reg 类型这一问题，这里给出一个简单的解决方法：

always 中设计的信号都定义为 reg 类型，其他信号都定义为 wire 类型

注意：这个方法只适合与 FPGA 入门的新手，当我们需要更加复杂的信号的时候，我们就需要进一步判读我们所需要的信号类型，这个方法就不奏效了