Embedded software test preparation_1 computer system foundation

Embedded soft test preparation

1. Basics of computer systems

4 points or so. But it is the basis of problem solving.

number conversion

Needless to say about base conversion. Mainly decimal, binary, octal, hexadecimal.

binary arithmetic operations

The first is bit B KB MB GB, and 01 addition, subtraction, multiplication and division.

Address difference+1=380000H bit. Convert to KB unit.

Be sure to see Byte and bit clearly!

representation of numbers

original code complement code

Original code: the first digit of a negative number is 1. For example -1: 1000 0001.

Negative code: Invert all negative numbers except the sign bit. Such as -1:1111 1110.

Complement code: Negative number inverse code +1. For example -1: 1111 1111.

Frame shift: Invert the sign bit of the complement code. Such as 1: 1000 0001, -1: 0111 1111.

One's complement and two's complement are used to implement the subtraction operation. However, the result of one's complement operation may have meaningless -0. The complement code will not.

The range of the original code and the inverse code is $-2^{n-1}-1$ ~ $2^{n-1}-1$ , n-1 is because one bit is the sign bit.

The representation range of complement code and frame shift is $-2^{n-1}$ ~ $2^{n-1}-1$ , because the inverse code of the original code has -0, and the complement code does not. For example, the complement code of 1000 0000 can represent -128.

Frame shifting is usually used to represent exponents of floating-point numbers.

The complement code is converted back to the original code is to invert first and then +1.

fixed point floating point

Fixed number of points: fixed decimal point.

Fixed point integer: 123000.

Fixed point decimal: 123.000

Floating point numbers: $N=R^e\ast M$ , M is the mantissa, R is the base, and e is the exponent.

The storage structure includes: order sign, order code, number sign and mantissa.

Calculation of the order code: first check the order, and then adjust the mantissa after the calculation.

computer composition

Five major parts, arithmetic unit, controller, memory, input device, and output device.

Registers under the operator

Arithmetic Logic Unit ALU: Arithmetic and logical operations on data.

Accumulation Register AC: general purpose register for residual data.

Data buffer register DR: When reading and writing memory, temporarily store instructions or data.

Status condition register PSW: stores status flags and control flags. Such as overflow.

Registers under the controller

Program Counter PC: Stores the address of the next instruction to be executed.

Instruction register IR: stores the instruction to be executed.

Instruction Decoder ID: Analyze and interpret instructions.

Timing component: Provides the opcode field in the timing control signal instruction.

Example: A computer instruction includes an operation code and an address code. Where are these two parts stored?

A: Both are stored in the IR. Although it is an address, it is not the address corresponding to the instruction, but the address corresponding to the data to be operated by the instruction, which is a part of the instruction.

Measuring Computer Performance Indicators

CPU：

Main frequency: The higher the speed, the faster it will run.

Word length: the data that can be processed. Corresponds to the number of CPU bits.

CPU cache: Temporarily stored data.

Number of cores: Process concurrency.

Bus: data bus, control bus, address bus.

• Bandwidth: The data that can be processed per unit of time.
• Bit Width: Data bus width.
• Working frequency: several cycles/s. Bandwidth = bit width * operating frequency.

The answer is C.

BIOS/CMOS: Save some configuration information of the computer. BIOS configuration CMOS in RAM is ROM; CMOS stores some modifiable BIOS parameters, such as boot date setting, software startup sequence, password, etc.

System performance evaluation method:

Clock frequency: similar to the main frequency.

Instruction execution speed: How many instructions per second are usually only calculated with basic addition instructions.

Equivalent instruction speed method: Calculate the equivalent time after averaging a certain proportion of various instructions.

Data processing rate PDR.

Core program method, benchmark test program: use program to test speed.

instruction

It consists of opcode and operand address code.

For example, a four-address instruction may be in the form of: addition instruction, addend 1 address, addend 2 address, answer address, next instruction address.

Simplification: the address of the next instruction is placed in pc.

Simplify again: put the operation result in the accumulation register ACC.

An address command: for example, read the data in the address.

Zero-address instructions: no-argument instructions such as popping and pushing.

addressing mode

In order to expand the addressing space and improve programming flexibility, many addressing modes have emerged.

Immediate addressing: The operands are placed in the instruction. Poor flexibility.

Direct addressing: The address where the operand is stored in the instruction.

Indirect addressing: An address pointing to the address of the operand is placed in the instruction.

Register addressing mode: the register puts the operand.

Register indirect addressing mode: The address of the operand is placed in the register.

assembly line

Each instruction needs to go through three stages of instruction fetching-analysis-execution. We can overlap the processing of different stages, quasi-parallel implementation.

Calculation formula: execution time of one instruction + (number of instructions - 1) * pipeline cycle. The pipeline cycle is the longest execution time in fetching, analyzing, and executing.

Pipeline throughput rate: the reciprocal of the total time spent.

Pipeline maximum throughput: the reciprocal of the pipeline cycle.

Example: Fetch 2ns, analyze 2ns, execute 1ns, what is the pipeline cycle? What is the shortest time for 100 instructions?

Answer: 2ns; (5ns) + (99) * (2ns) = 203ns.

multi-level storage

The upper one is small, fast, but expensive; the lower one is big, slow, and cheap. Lets say the above is the cache below.

cache: There is a piece of storage space and an associative storage table. Cache is mainly to optimize the time and space locality of the program to speed up the access speed.

Average system access cycle: Assuming that the probability of hitting the cache is h, the cache access time is t1, and the memory access time is t2, the average cycle is ht1+(1-h)t2

cache direct image

Cache on the left and main memory on the right.

Each part of the main memory is divided into: the main memory area number, the block number in the area, and the address in the block.

When the main memory is cached in the cache, it must be cached in the same block number. For example, the first block in the 0th area, the 1st area, and the 2nd area... can only be cached in the first block in the cache.

We judge whether it is a hit, for example, we want to find the fourth block in the third area. Let's see if there is any cached data in the fourth block in the cache, and if so, whether the main storage area number is the third area. Hit if yes.

This method has a simple address conversion circuit and fast access speed, but is prone to conflicts, has a low hit rate, has high requirements for page replacement algorithms, and has low space utilization.

Fully associative address mapping and translation

Any piece of main memory can be placed anywhere in the cache. The space utilization rate and the hit rate are high, but the implementation is complicated and the speed is slow. Suitable for small capacity cache.

Set-associative address mapping and translation

The cache is divided into several groups, and the main memory is partitioned according to the number of cache groups. For example, the cache is divided into 8 groups, each group has 2 units, then the main memory is divided into several 8-group areas, the first group of each area is stored in the first group of the cache, and the second group is stored in the second group of the cache Group……

It is a compromise between the direct image and the fully associative address image, and the implementation difficulty and hit rate are also between the two.

I/O control

Direct program control: including unconditional transfer mode and program query mode.

Unconditional transfer: The CPU is always preparing to access the external device, and can access it immediately when it needs access.

Program inquiry method: CPU continuously inquires whether the external device is free, and can be used only when it is free. For example, if you want to print 12345, the CPU first checks to see if the printer is free, and then prints 1 first when it is free. After a while, it checks to see if it is free after printing. If it is not free, it waits again, and then prints 2 when it is free...

The disadvantage is that the CPU has to wait for IO all the time.

Interrupt mode: the printer will send an interrupt to the CPU after printing, and the CPU will know that the printer can be called after receiving it. In this way, the CPU does not have to keep checking whether the IO device is idle.

But this method still occupies a bit of CPU, because the print data is still sent to the printer by the CPU.

Direct memory reading method DMA: When printing, the CPU sends the data to the direct memory, and then you don’t have to stay with the printer until the end of the printing, you can do other things. Only intervenes when IO starts and ends.

Input and output processor IOP: Commonly used by large hosts, you can understand it through channels.

reliability and checksum

reliability

Master the calculation formulas of various system reliability. Generally speaking, it is a mixed system.

Simply put, serial is * reliability, and parallel is * failure rate.

check code

Code Distance: The minimum distance between two legally encoded codewords in an encoding system. 2 bits are error detectable. 3 bits are error correctable.

Parity can only detect errors (one-bit error detection), CRC can detect multiple-bit errors, and Hamming code can detect and correct one-bit errors.

The parity check code needless to say.

CRC: k data bits followed by r check bits for encoding. Just understand the concept.

Hamming code: Insert k check digits between data bits, requiring $2^k-1\ge n+k$ 。