PubMed | Composition Principle [Chapter 2] Data Representation and Operation
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- PubMed | Composition Principle [Chapter 2] Data Representation and Operation
- I. Number system and coding
- II. Calculation method and circuit
- III. Representation and operation of floating point numbers
I. Number system and coding
a. Carry counting system and its mutual conversion
- Integer part converted from decimal to binary:Pay attention to the high and low order
- Decimal to binary conversion:Watch out for high-status sorting
b. BCD code
BCD code:It is Binary-Coded Decimal, which is a binary-coded decimal number
1. 8421 yards
Code 8421:That is, each number from 0 to 9 is expressed one by one with 4-bit binary numbers; among them, the 8421 code is also called the right code , counting from left to right, the weight of the first 1 is 8; the weight of the second 1 is 4; the third 1 has a weight of 2; the fourth 1 has a weight of 1;
decimal | 5 | + | 8 | = | 1 | 3 |
---|---|---|---|---|---|---|
binary | 0101 | + | 1000 | = | 0001 | 0011 |
2. The remaining 3 yards
3 yards left:It belongs to the unrighted code , which is based on the 8421 code, adding ( 3 ) 10 (3)_{10} to each bit(3)10, which is binary (0011) 2 (0011)_2(0011)2
3. 2421 yards
Code 2421:Same as the 8421 code, both belong to the weighted code , but different from the 8421 code, counting from right to left, each 1 has a weight of 2421
c. Unsigned integer representation and operation
1. Express
- All binary bits are value bits, no sign bit , the iiThe bit weight of i bit is 2 i − 1 2^{i-1}2i−1
- n n n bit unsigned integer represents the range0 ∼ 2 n − 1 0\sim2^{n}-10∼2n−1 , overflow if exceeded
- The minimum number is all 0s; the maximum number is all 1s
2. Operation
- addition:Starting from the lowest bit, add bit by bit, and carry to a higher bit
- Subtraction:
- "Minuend" remains unchanged, all bits of "subtrahend" are reversed bit by bit, the last bit is +1 (that is, complement code), subtraction becomes addition
- Starting from the lowest bit, add bit by bit, and carry to a higher bit.
d. Representation and operation of signed integers
1. Original code
For n + 1 n+1n+1 -bit machine word length:
- The highest bit is the sign bit, "0/1" corresponds to "positive and negative"; the remaining bits are value bits, which represent the absolute value of the true value
- Indicates the range − ( 2 n − 1 ) ≤ x ≤ 2 n − 1 -(2^n-1) \leq x \leq 2^n-1−(2n−1)≤x≤2n−1
- The truth value 0 has two forms , [ + 0 ] original = 0 , 00000000 ; [ − 0 ] original = 1 , 00000000 [+0]_original=0,00000000; [-0]_original=1,00000000[+0]Original=0,00000000;[−0]Original=1,00000000
Disadvantages: The sign bit cannot participate in the operation, and complex hardware circuits need to be designed to process it
2. Inverse code
On the basis of the original code: the positive number remains unchanged; the sign bit of the negative number remains unchanged, and the value bit is reversed
3. Complement
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Machine way:Original → Inverse → Complement ( inverse code to complement code: positive numbers remain unchanged, negative numbers + 1 at the end )
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Manual calculation method:Original → complement
Positive numbers remain unchanged; negative numbers find the first 1 from right to left, and all the digits to the left of this 1 are reversed bit by bit;
the same method is used to convert complement codes to original codes, positive numbers remain unchanged, and negative numbers move from right to left Find the first 1 on the left, and all the value bits to the left of this 1 are bitwise inverted
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Here is a method that I summed up to calculate the truth value directly from the complement of negative numbers:
See the blue part in the lower right corner of the above picture- Find the first 1 from right to left
- The binary weight corresponding to all 0s to the left of this 1 + the binary weight corresponding to this 1 = true value
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Two's complement addition:Starting from the lowest bit, add bit by bit (including the sign bit), and carry to a higher bit
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Two's complement subtraction:
- The "minuend" remains unchanged, and the "subtrahend" is all bitwise inverted ( including the sign bit ), and the last bit is +1
- Subtraction becomes addition, starting from the lowest bit, adding bit by bit, and carrying to a higher bit
4. Frameshift
Frameshift:On the basis of complement code, the sign bit is reversed; Note: only positive numbers can be represented
5. Comparison of original negative complement and frame-shift characteristics
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Conversion relationship:
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Indicates the range:
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Several codes are used to represent integers:
e. Representation and operation of fixed-point decimals
1. Fixed Point Decimal vs Fixed Point Integer
Note: The first digit of the fixed-point decimal is the sign bit, that is, the digit before the decimal point; the fixed-point decimal cannot be represented by shifting
2. Addition of fixed-point decimals
Same as fixed-point integer addition: start from the lowest bit, add bit by bit (including the sign bit), and carry to a higher bit;
3. Subtraction of fixed-point decimals
Same as fixed-point integer subtraction: "minuend" remains unchanged, all bits are reversed bit by bit, the last bit is +1, subtraction becomes addition
II. Calculation method and circuit
a. Basic computing components
1. Logical operations
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with|or|not
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AND NOT| OR NOT| DIFFERENT AND NOT| SAME OR
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Implement XOR gates with NOR combinations
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Simplify logical expressions
- Priority: with > or
- 电影律: A ( C + D ) = AC + ADA(C+D)=AC+ADA(C+D)=AC+AD
- Associativity: ABC = A ( BC ) ABC=A(BC)ABC=A ( B C ) ; A + B + C = A + ( B + C ) A+B+C=A+(B+C)A+B+C=A+(B+C)
- 反演律: A + B ‾ = A ‾ ⋅ B ‾ \overline{A+B}=\overline{A}\cdot\overline{B} A+B=A⋅B; A ⋅ B ‾ = A ‾ + B ‾ \overline{A\cdot B}=\overline{A}+\overline{B} A⋅B=A+B
2. One-bit full adder
The function implemented by a full adder is an addition on a binary bit, not only combining the binary bits of the current two addends, but also combining the carry from the previous binary bit.
- Addition result S i S_iSi: See if there are even or odd 1s in the input (the binary bits of the two addends and the carry of the previous bit)
S i = A i ⊕ B i ⊕ C i − 1 S_i = A_i \oplus B_i \oplus C_{ i-1}Si=Ai⊕Bi⊕Ci−1 - Carry to high bit C i C_iCi: If there are at least two 1s in the input, the carry is 1
C i = A i B i + ( A i ⊕ B i ) C i − 1 C_i = A_iB_i+(A_i\oplus B_i)C_{i-1}Ci=AiBi+(Ai⊕Bi)Ci−1
The first item represents that the binary bits of both addends are 1,
and the second item represents that only one of the two basic bits is 1, and the carry from the lower bit is 1
Expressed in a logic circuit diagram:
3. Serial Adder
Serial adder: It is only composed of a one-bit full adder. The two addends are sent to the full adder bit by bit for operation. This is serial. If the operand is nn longn bits, the adder will performnnn operations.
4. Parallel adder with serial carry
Parallel adder with serial carry: put nnWhen n full adders are connected in series, twonnThe result of the addition of n -bit binary numbers
can be seen from the figure. The disadvantages are obvious. Since the input of each stage includes the carry of the previous bit in addition to the binary numbers of the two addends itself, the input of each stage Addition depends on the upper level.
5. Parallel adder with parallel carry
The parallel adder with parallel carry is actually playing some tricks on a serial basis. As mentioned earlier, due to the limitation of carry C i − 1 C_{i-1} at each stageCi−1, so we have C i C_{i}Ci 进行展开:
C i = A i B i + ( A i ⊕ B i ) C i − 1 C i = A i B i + ( A i ⊕ B i ) ( A i − 1 B i − 1 + ( A i − 1 ⊕ B i − 1 ) C i − 2 ) C i = A i B i + ( A i ⊕ B i ) ( A i − 1 B i − 1 + ( A i − 1 ⊕ B i − 1 ) ( A i − 2 B i − 2 + ( A i − 2 ⊕ B i − 2 ) C i − 3 ) ) \begin{aligned} &C_{i}=A_{i} B_{i}+\left(A_{i} \oplus B_{i}\right) C_{i-1} \\ &C_{i}=A_{i} B_{i}+\left(A_{i} \oplus B_{i}\right)\left(A_{i-1} B_{i-1}+\left(A_{i-1} \oplus B_{i-1}\right) C_{i-2}\right) \\ &C_{i}=A_{i} B_{i}+\left(A_{i} \oplus B_{i}\right)\left(A_{i-1} B_{i-1}+\left(A_{i-1} \oplus B_{i-1}\right)\left(A_{i-2} B_{i-2}+\left(A_{i-2} \oplus B_{i-2}\right) C_{i-3}\right)\right) \end{aligned} Ci=AiBi+(Ai⊕Bi)Ci−1Ci=AiBi+(Ai⊕Bi)(Ai−1Bi−1+(Ai−1⊕Bi−1)Ci−2)Ci=AiBi+(Ai⊕Bi)(Ai−1Bi−1+(Ai−1⊕Bi−1)(Ai−2Bi−2+(Ai−2⊕Bi−2)Ci−3))
When expanded to C 0 C_0C0When , the overall C i C_iCican be determined directly, because each bit of A i A_iAi B i B_i BiAlready, C i C_iCiIt is also known, then you can directly calculate the carry C i C_i of any stepCi
We repeat G i = A i B i G_i=A_iB_iGi=AiBi P i = A i ⊕ B i P_i=A_i\oplus B_i Pi=Ai⊕Bi
C i = A and B i + ( A i ⊕ B i ) C i − 1 = G i + P i C i − 1 C 1 = G 1 + P 1 C 0 C 2 = G 2 + P 2 C 1 = G 2 + P 2 G 1 + P 2 P 1 C 0 C 3 = G 3 + P 3 C 2 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 C 0 C = G 4 + P 4 C 3 = G 4 + P 4 G 3 + P 4 P 3 G 2 + P 4 P 3 P 2 G 1 + P 4 P 3 P 2 P 1 C 0 \begin{aligned} &C_{ i}=A_{i}B_{i}+\left(A_{i}\plus B_{i}\right) C_{i-1}=G_{i}+P_{i}C_{i-1} \\&C_{1}=G_{1}+P_{1} C_{0} \\&C_{2}=G_{2}+P_{2} C_{1}=G_{2}+P_{2} G_{1}+P_{2} P_{1} C_{0} \\&C_{3}=G_{3}+P_{3} C_{2}=G_{3}+P_{3} G_{2 }+P_{3}P_{2}G_{1}+P_{3}P_{2}P_{1}C_{0}\\&C_{4}=G_{4}+P_{4}C_{3 }=G_{4}+P_{4} G_{3}+P_{4} P_{3} G_{2}+P_{4} P_{3} P_{2} G_{1}+P_{4} P_{3} P_{2} P_{1} C_{0} \end{aligned}Ci=AiBi+(Ai⊕Bi)Ci−1=Gi+PiCi−1C1=G1+P1C0C2=G2+P2C1=G2+P2G1+P2P1C0C3=G3+P3C2=G3+P3G2+P3P2G1+P3P2P1C0C4=G4+P4C3=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1C0
Draw a circuit diagram:
6. Complementary addition and subtraction
- XY corresponds to two addends or minuend and subtrahend respectively
- set sub subs u b , set to 1 if it is subtraction, and set to 0 if it is addition
- 当 s u b sub s u b is 0, that is, when adding, Y directly enters the adder through the multiplexer
- 当 s u b sub s u b is 1:
- Y will go through the NOT gate first, and perform bitwise inversion on all the bits on Y
- At the same time, sub subs u b as 1, also asC i − 1 C_{i-1}Ci−1into the adder
- Invert all the bits of Y and then +1 to complete the operation from XY to X+(-Y)
7. Flag generation
b. Shift operations of fixed-point numbers
1. Arithmetic shift
2. Logical shift
- Logical right shift:Fill high bits with 0, discard low bits
- Logical left shift:Fill low bits with 0, discard high bits
3. Cyclic shift
c. Multiplication of fixed-point decimals
1. Original code multiplication
- The sign bit is processed separately, sign bit = xs ⊕ ys = x_s\oplus y_s=xs⊕ys
- The absolute value of the numeric digits is multiplied:
- First review the components of several calculators:
- We now want to calculate: [ x ] original = 1.1101 , [ y ] original = 0.1011 , x ⋅ y [x]_original=1.1101, [y]_original=0.1011, x\cdot y[x]Original=1.1101,[y]Original=0.1011,x⋅y
- First change the sign bit of the multiplicand, namely x, to 0, take the absolute value, and put it into the general register XXThe multiplier in X
, that is, y, the sign bit also takes 0, takes the absolute value, and puts it into the multiplication quotient registerMQ MQM Q accumulatorACC
ACCA C C all set to 0;
- Looking at the multiply quotient register MQ MQ from right to leftM Q , the first one is1 11
then we go to accumulatorACC ACCAdd general-purpose registerXX to A C CMultiplicand XXin XX
then accumulatorACC ACCA C C and multiplication quotient registerMQ MQM and Q logically shift right together: the high bit is complemented with0 00 , discard low bits - Then repeat the fourth step, still 1 11 , so we add to the accumulatorACC ACCA C C first add general registerXXMultiplicand in X , then ACC ACCA C C andMQ MQM Q logical shift right together:
- Continue to repeat the fourth step, but this time it is 0 00 , if encounter0 00 , accumulatorACC ACCA C C does not add anything, and directly adds to the multiplication quotient registerMQ MQM Q logical shift right
- Repeat the fourth step until the multiplication quotient register MQ MQ that originally put the multiplierThe sign in MQ is shifted to the last bit, and it can be stopped. AtACC ACC
needs to beThe first bit of A C C , that is, the sign bit is changed to the first sign bit= xs ⊕ ys = x_s\oplus y_s=xs⊕ys
Then accumulator ACC ACCA C C and multiplication quotient registerMQ MQThe numbers combined by M and Q are the result of the final product
- Simplifying the above process into a hand calculation process is like this:
2. Two's complement multiplication
- Complement multiplication is similar to original multiplication, but there are differences:
- In the operation of two's complement multiplication:
- The machine word length of all registers is unified n + 2 n+2n+2 bits, using double sign bit to represent complement code.
- Multiply Quotient Register MQ MQIn MQ , the single sign bit is used to represent the multiplier's complement, and the last machine bit is placed in the auxiliary bit, which is initially 0
- Auxiliary bits - MQ MQThe lowest bit in M Q = 1,( ACC ) + [ x ] Complement (ACC)+[x]_complement(ACC)+[x]Supplement
Auxiliary bits - MQ MQThe lowest bit in M Q = 0,( ACC ) + 0 (ACC)+0(ACC)+0
auxiliary bit -MQ MQThe lowest bit in M Q = -1,( ACC ) + [ − x ] Complement (ACC)+[-x]_complement(ACC)+[−x]Supplement - After addition, ACC ACCA C C andMQ MQArithmetic shift right with M and Q
- Move to the right until it is originally placed in the multiplication quotient register MQ MQAfter the sign bit of the multiplier of M Q , one more addition has to be performed
- Last accumulator ACC ACCA C C and multiplication quotient registerMQ MQM Q together form the final product (signed bit)
d. Division of fixed-point decimals
1. Original code division operation
1-1. Recovery remainder method
- General register XXX store divisor
accumulatorACC ACCA C C stores the dividend Multiplication
quotient registerMQ MQM Q storage result quotient - The sign bit handles xs alone ⊕ ys x_s \oplus y_sxs⊕ys
- Put the corresponding divisor and dividend into the general register XXX , accumulatorACC ACCA C C , multiplication quotient registerMQ MQSet M Q to 0
- Every round, direct no-brained quotient 1 11
- Find the remainder: ( ACC ) − (divisor) → ACC (ACC)-(divisor)\rightarrow ACC(ACC)−( divisor )→ACC
- Discover ACC ACCIn A C C , the remainder is a negative number, and the quotient is changed to0 00
- Change the quotient to 0 0After 0 ,ACC ACCA C C should also be changed back, so( ACC ) + (divisor) → ACC (ACC)+(divisor)\rightarrow ACC(ACC)+( divisor )→A C C , this step is called recovering the remainder
- Then ACC ACCA C C andMQ MQM Q overall logical shift left
- Repeat steps 1~5 until the multiplication quotient register MQ MQAll machine bits in MQ have a definite quotient
- Finally got the result
- Summary: Look at the flow chart
1-2. Alternate addition and subtraction method (non-recovery remainder method)
- main idea:
- Overall process:
2. Complementary division operation
- Essence:
- There is a classic question:
- If you don't study this question deeply, you can choose BB directlyB , should be the multiplication and division of complement code, the key step is that the sign bit participates in the operation
- If you dig deeper:
- What is subtraction: the absolute value of the minuend is greater than the absolute value of the subtrahend
- Dividing the same sign:
find the remainder Enough to reduce business Not enough to reduce business subtraction Divisor and remainder have the same sign 1 divisor and remainder 0 - Get along with different signs:
find the remainder Enough to reduce business Not enough to reduce business addition divisor and remainder 0 Divisor and remainder have the same sign 1 - Such as: dividend -3, divisor -2 and +2, enough to subtract
- − 3 has the same sign as − 2 ⇒ − 3 − ( − 2 ) = − 1 ⇒ the remainder and the divisor have the same sign ⇒ the quotient 1 -3 has the same sign as -2\Rightarrow -3 - (-2) = -1 \Rightarrow sum of remainders divisor same sign\Rightarrow quotient 1− 3 with−2 same number⇒−3−(−2)=−1⇒Remainder and divisor have the same sign⇒Quotient 1
- − 3 and + 2 different sign ⇒ − 3 + ( + 2 ) = − 1 ⇒ remainder and divisor different sign ⇒ quotient 0 -3 and +2 different sign \Rightarrow -3+(+2)=-1 \Rightarrow remainder sum divisor with different sign\Rightarrow quotient 0− 3 with+2 different signs⇒−3+(+2)=−1⇒Remainder and divisor with different signs⇒Quotient 0