m FPGA-based AGC adaptive gain control system verilog implementation, including testbench - Code World

m FPGA-based AGC adaptive gain control system verilog implementation, including testbench

Enterprise 2023-05-17 10:08:52 views: null

NoSuchKey

Guess you like

Origin blog.csdn.net/hlayumi1234567/article/details/130651500

m FPGA-based AGC adaptive gain control system verilog implementation, including testbench

m Verilog implementation of FPGA-based QPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m Verilog implementation of FPGA-based BPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m FPGA-based CRC cyclic redundancy check system verilog implementation, including testbench

m Verilog implementation of FPGA-based interleaving and deinterleaving system, including testbench

m Verilog implementation of FPGA-based DQPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m FPGA-based 4ASK modem system verilog implementation, including testbench test files

m FPGA-based 8PSK modulation and demodulation system verilog implementation, including testbench test files

m FPGA-based 8ASK modem system verilog implementation, including testbench test files

m FPGA-based 8FSK modem system verilog implementation, including testbench test files

m FPGA-based 4FSK modem system verilog implementation, including testbench test files

m FPGA-based OFDM modulation and demodulation system verilog implementation, including IFFT, FFT and shaping filters, including testbench

m FPGA-based OFDM system verilog implementation, including IFFT, FFT, shaping filtering and CP addition and CP removal, including testbench

m FPGA-based data serial-to-parallel conversion system verilog implementation, including testbench, can configure the number of parallel

m FPGA-based Gaussian white noise channel simulation system verilog implementation, including testbench, can be configured with different SNR and frequency offset

m FPGA-based FOC controller verilog implementation, including CLARK, PARK, PID and SVPWM, including testbench

m FPGA-based basic OFDM modulation and demodulation verilog implementation, including IFFT and FFT, including testbench

m FPGA-based communication data frame scrambling and descrambling verilog implementation, including testbench

m FPGA-based 1024QAM modulation signal generation module verilog implementation, including testbench

m FPGA-based 256QAM modulation signal generation module verilog implementation, including testbench

m FPGA-based QPSK soft demodulation verilog implementation, including testbench and MATLAB auxiliary verification program

m FPGA-based 16QAM soft demodulation verilog implementation, including testbench

[AGC+FPGA] FPGA-based digital AGC adaptive gain design, applied in BPSK modulation and demodulation system

m FPGA-based LDPC minimum sum decoding algorithm verilog implementation, including testbench and matlab auxiliary verification program

m FPGA-based implementation of phase estimation and compensation algorithm for QPSK modulated signal with phase deviation in verilog, including testbench

m FPGA-based verilog implementation of phase estimation and compensation algorithm for 64QAM modulated signal with phase deviation, including testbench

m FPGA-based 256-point FFT Fourier transform verilog implementation, including testbench, without using IP core

m FPGA-based implementation of costas ring carrier synchronization verilog, including testbench, which can modify the frequency offset

m Implementation of PAPR reduction technology in FPGA-based OFDM system, including testbench test files and MATLAB auxiliary testing

Adaptive PI controller design based on FPGA-based online real-time adjustment of control parameters, including testbench test program

Recommended

Ranking

Dynamic Monitoring matplotlib plotted CUP 1 minute (60s) of the python

Fortunately, the latest 2019 [airship] formula racing rule 567 yards formula plan skills practical skills Wynn does not lose time acquisition function

R Notes - Chapter 2 Simple Operations of R

Go os.Stdin: Pointer to the standard input file

Design of Intelligent Unmanned Patrol Car Based on Raspberry Pi 4B-Reply PPT

Windows Driver Development - reading and writing equipment

Use spring interceptor for ip white list & basic authorization verification

The similarities and differences between BeanFactory and ApplicationContext

JMeter - Velocity JSR223 script can't use JMeter variables/environment

About ports and processes

Daily

More

2025-02-24(0)

2025-02-23(0)

2025-02-22(0)

2025-02-21(0)

2025-02-20(0)

2025-02-19(0)

2025-02-18(0)

2025-02-17(0)

2025-02-16(0)

2025-02-15(0)