Single-chip microcomputer principle and application fourth edition Lin Li after-school multiple-choice questions

Answers to Chapter 1 Multiple Choice Questions

(1) Single-chip microcomputer is also called single-chip microcomputer, and the initial English abbreviation is ___D___.
   A.MCP B.CPU C.DPJ D.SCM
(2) Intel's MCS-51 series single-chip microcomputer is ____C__ single-chip microcomputer.
   A.1 bit B.4 bit C.8 bit D.16 bit
(3) What is not included in the characteristics of the single chip microcomputer is ___C___.
   A. High integration B. Low power consumption C. Strong sealing D. High cost performance
(4) What is not included in the development trend of single-chip microcomputer is __B____. A. High performance B. High
   price C. Low power consumption D. High cost performance
(5) The binary number of the decimal number 56 is A.
   A.00111000B B.01011100B C.11000111B D.01010000B
(6) The binary number of the hexadecimal number 93 is ___A___.
   A.10010011B B.00100011B C.11000011B D.01110011B
(7) The hexadecimal number of the binary number 11000011 is ___B___.
   A. B3H B.C3H C.D3H D.E3H
(8) The decimal unsigned number of the binary number 11001011 is __B____.
   A. 213 B.203 C.223 D.233
(9) The signed decimal number of the binary number 11001011 is ___B___.
   A. 73 B.-75 C.-93 D.75
(10) The 8421BCD compression code of the decimal number 29 is ____A__.
   A. 00101001B B.10101001B C.11100001B D.10011100B
(11) The complement and complement of the decimal number -36 in an 8-bit microcomputer is ____D__.
   A. 00100100B, 11011100B B. 00100100B, 11011011B
   C. 10100100B, 11011011B D. 11011011B, 11011100B
   The inverse code of a negative number keeps the sign bit unchanged, and the inverse
    code of the other seven bits is based on the inverse code +1
    -36 Original code 10100100
    Inverse code 11011011
    Complement code 11011100
(12) The complement code and complement code of the decimal number +27 in the 8-bit microcomputer are ___C___ respectively.
   A.00011011B, 11100100B B.11100100B, 11100101B
   C.00011011B, 00011011B D.00011011B, 11100101B
   The complement and complement of positive numbers are the same as their original codes
(13) The ASCII code for character 9 is ____D__.
The ASCII code for character 9 is 57
   A. 0011001B B.0101001B C.1001001B D.0111001B
(14) The corresponding character of ASCII code 1111111B is ___C___.
   A. SPACE BP C.DEL D.{ (15) OR The expression of logic is ___B___.    AA⋅B=F B. A+B=F C. A⊕B=F D.(A⋅B) ⃗=F (16) The expression of XOR logic is __C____.    AA⋅B=F B. A+B=F C. A⊕B=F D.(A⋅B) ⃗=F (17) "AND", "OR" and "XOR" of binary numbers 10101010B and 00000000B The result is __B____.    A. 10101010B, 10101010B, 00000000B B. 00000000B, 10101010B, 10101010B    C. 00000000B, 10101010B, 00000000B D. 10101010B, 00000000B, 101 01010B (18) "AND", "OR" and "XOR" results of binary numbers 11101110B and 01110111B It is ____D__.    A.01100110B, 10011001B, 11111111B B.11111111B, 10011001B, 01100110B    C.01100110B, 01110111B, 10011001B D.01100110B, 11111111B, 1001100 1B (19) Among the following integrated gate circuits, the one with AND gate function is ___D___.











    A. 74LS32 B. 74LS06 C. 74LS10 D. 74LS08
(20) Among the following integrated gate circuits, the one with the function of NOT gate is ____B__.
   74LS32 B. 74LS06 C. 74LS10 D. 74LS08
(21) Proteus software consists of the following two design platforms____C__.
   A. ISIS and PPT B. ARES and CAD C. ISIS and ARES D. ISIS and CAD
(22) The main function of the ISIS module is ___A___.
   A．Circuit schematic design and simulation B. Advanced wiring and editing C. Image processing D. C51 source program debugging
(23) The main function of the ARES module is __B____.
   A．Circuit schematic design and simulation B. Advanced wiring and editing C. Image processing D. C51 source program debugging
(24) The single-chip microcomputer used in household appliances such as refrigerators, air conditioners, and washing machines mainly uses its __D____ ability.
   A．High-speed calculation B. Mass storage C. Long-distance communication D. Measurement control

Chapter 2 Multiple Choice Questions

(1) The following description about the program counter PC is wrong.C

A. PC is not a special function register B. The count value in PC can be modified by programming instruction

C. PC can address 64KB RAM space D．The first address of the next instruction is stored in the PC

(2) The reset signal of the MCS-51 microcontroller is valid.D

A, falling edge B, rising edge C, low level D, high level

(3) The first of the following optionsAItem is not the basic configuration of 80C51 microcontroller.

A. Timer/counter T2 B. 128B on-chip RAM C．4KB on-chip ROM D．Full-duplex asynchronous serial port

(4) The CPU in the single-chip microcomputer is mainly composed ofBIt consists of two parts.

A. Arithmetic units and registers B. Arithmetic and controller C. Arithmetic unit and decoder D. Arithmetic Units and Counters

(5) Among the following special function registers of the 51 single-chip microcomputer, the one with a 16-bit word length isD。

A．PCON B．TCON C． SCON D．DPTR

(6) The ALE pin of 80C51 microcontroller isApin.

A．Address latch enable output B. External program memory address enable input C. Serial communication port output D. Reset signal input terminal
(7) The memory of the 80C51 single-chip microcomputer is a Harvard structure, which includesA。

A．4 physical spaces or 3 logical spaces B. 4 physical spaces or 4 logical spaces

C．3 physical spaces or 4 logical spaces D. 3 physical spaces or 3 logical spaces

(8) In the general-purpose I/O mode, before reading the pin level from the P1 port, you shouldB 。

A. Write 0 to port P1 first. B. First write 1 to P1 port C. First clear the interrupt flag D. open interrupt first

(9) The symbol of the flag bit reflecting the carry (or borrow) state in the program status word register isA。

A．CY B. F0 C . OV D. AC

(10) The program counter PC in the microcontroller is used toC。

A. Store the instruction B. Store the address of the instruction being executed

C. Store the address of the next instruction D. Store the address of the previous instruction

(11) After the microcontroller is powered on and reset, the contents of PC and SP areB。

A．0000H，00H B. 0000H，07H C . 0003H，07H D. 0800H，08H

(12) 80C51 MCU should use on-chip RAM, /EA pinD。

A. Must be connected to +5V B. Must be grounded C. Must be floating D. No limit

(13) RS1 and RS0 in PSW are used toA。

A. Select working register area number B. Indicate reset C. Select timer D. Select interrupt mode

(14) After power-on reset, the initial value of PSW isD。

A.1 B. 07H C . FFH D. 0

(15) The XTAL1 and XTAL2 pins of the microcontroller 80C51 areDpin.

A. External timer B. External serial port C. External interrupt D. External crystal oscillator

(16) The VSS(20) pin of 80C51 MCU isBpin.

A．Main power +5V B. Ground C. Backup power D. Access off-chip memory

(17) Among the P0~P3 ports of the 80C51 single-chip microcomputer, the ports with the second functionD 。

A．P0 B. P1 C . P2 D. P3

(18) When the /EA pin of the 80C51 MCU is connected to +5V, the effective address range of the program counter PC isD。

A．1000H～FFFFH B. 0000H～FFFFH C .0001H～0FFFH D.
0000H～0FFFH

(19) When R0 and R1 in the program status word register PSW are 0 and 1 respectively, the working register group selected by the system isC。

A．Group 0 B. Group 1 C. Group 2 D. Group 3

(20) The byte address range with bit address in the internal RAM of 80C51 microcontroller isB。

A．0～1FH B. 20H～2FH C .30H～5FH D. 60H～7FH

(21) If the machine cycle of 80C51 microcontroller is 12 microseconds, then its crystal oscillator frequency isA MHz。

A．1 B．2 C．6 D．12

(22) The internal program memory capacity of 80C51 MCU isC。

A.16K B.8K C.4K D.2K

(23) The reset function pin of 80C51 MCU isC。

A.XTAL1 B.XTAL2 C.RST D.ALE

(24) The internal registers of 80C51 that reflect the program running status or operation result characteristics areB。

A. PC B. PSW C. A D.DPTR

(25) When PSW=18H, the current working register isD。
0001100

A. Group 0 B. Group 1 C. Group 2 D. Group 3

Chapter 3 Multiple Choice Questions

(1) The addressing mode with operands in the form of "@Ri" or "@DPTR" in the instruction is called a register.

A．Indexed addressing B. Indirect addressing c. direct addressing d. address immediately

(2) The assembly operation code that can realize the function of "decrement the operand by 1 first, and transfer to the target address if the result is still not zero" is
.

A．DJNZ BACJNE C．LJMP D．MOVX

(3) Given that P0 = #23H, the third bit can be set to 1 after executing the following instruction No. 1.

A．ADD P0,#34H B．ANL P0,#3BH C．ORL P0,#3BH D．MOV P0,#34H

(4) Among the following commands, the correct command that can access the external data memory is.

A.MOV A,@DPTR B.MOVX A,Ri C.MOVC A,@A+DPTR D.MOVX A,@Ri

(5) In the 80C51 assembly language instruction format, the only indispensable part is .

A. label B. opcode C. operand D. comment

(6) The following instructions to complete the data transfer of 80C51 on-chip RAM are.

A.MOVX A,@DPTR B.MOVC A,@A+PC C.MOV A,@Ri D.JMP @A+DPTR

(7) Among the immediate addressing instructions of 80C51, the immediate value is.

A. Contents placed in register R0 B. Constants placed in instructions C. Contents placed in A D. Contents placed in B

(8) Instruction JB 0E0H, 0E0H in LP refers to.

A. Accumulator A B. Highest bit of accumulator A C. Lowest bit of accumulator A D. A byte address

(9) The conditional transfer instruction in the following instructions refers to.

A.AJMP addr11 B.SJMP rel C.JNZ rel D.LJMP addr16

(10) 20H in 80C51 instruction MOV R0,20H refers to.

A. Immediate B. Byte address in internal RAM C. Bit address in internal RAM D.
Byte address in internal ROM

(11) Among the 80C51 instructions, the following instructions are unconditional branch instructions.

A.LCALL addr16 B.DJNZ direct,rel C.SJMP rel D.ACALL addr11

(12) Assuming A=0AFH, (20H)=81H, the result after executing the instruction ADDC A, 20H is .

A.A=81H B.A=30H C.A=0AFH D.A=20H

(13) It is known that A=0DBH, R4=73H, CY=1, the result after executing the instruction SUBB A, R4 is .

A.A=73H B.A=0DBH C.A=67H D.A=68H

(14) The following instruction judges if the content of the accumulator A is not 0, then switch to LP.

A.JB A,LP B.JNZ A,LP C.JZ LP D.DJNZ A,#0,LP

(15) Assuming that the accumulator A is an unsigned number and the number in B is 2, the functions of the following instructions are different from those of the other ones.

A.ADD A,0E0H B.MUL AB C.RL A D.RLC A

(16) The instruction that can rotate the content of A one bit to the left, and carry the 7th bit into the 0th bit.

A.RLC A B.RRC A C.RL A D.RR A

(17) Transfer the contents of the internal data storage unit 53H to the accumulator A, the instruction is.

A.MOV A,53H B.MOV A,#53H C.MOVC A,53H D.MOVX A,#53H

(18) The LJMP jump space is up to the maximum.

A.2KB B.256B C.128B D.64KB

(19) The purpose of properly using pseudo-instructions in programming is to instruct and guide.

A. How to manually assemble B. How to compile the program C. How to edit the source program D. How to program the programmer
(20) If you want to keep the high 4 bits of port P1 unchanged and reverse the low 4 bits, the available instructions are .

A.ANL P1,#0F0H B.ORL P1,#0FH C.XRL P1,#0FH D.MOV P1,#0FH

(21) The addressing mode for accessing off-chip data memory is.

A. Immediate addressing B. Register addressing C. Register indirect addressing D. Direct addressing

Answers to Chapter 5 Multiple Choice Questions

(1) The C51 statement that allows external interrupt 0 to interrupt is ______.
   A．RI=1; B．TR0=1; C．IT0=1; D．EX0=1;
(2) According to the natural priority order of interrupt sources, the lowest priority level is ______.
   A．External interrupt INT1 B．The serial port sends TI C．Timer T1 D．External interrupt INT0
(3) When the CPU responds to the timer T1 interrupt request, the address automatically loaded in the program counter PC is ______.
   A．0003H B．000BH C．0013H D．001BH
(4) When the CPU responds to the timer/INT0 interrupt request, the address automatically loaded into the program counter PC is ______.
   A．0003H B．000BH C．0013H D．001BH
(5) When the CPU responds to the timer/INT1 interrupt request, the address automatically loaded into the program counter PC is ______.
   A．0003H B．000BH C．0013H D．001BH
(6) Among the natural priorities of 80C51 MCU interrupts, the penultimate interrupt source is ______.
   A．External interrupt 1 B. Timer T0 C．Timer T1 D．External interrupt 0
(7) Among the natural priority levels of 80C51 MCU interrupts, the interrupt source with the second positive level is ______.
   A．External interrupt 1 B. Timer T0 C．Timer T1 D．Serial port TX/RX
(8) In order to make the external interrupt request signal appearing on the pin get CPU response, the condition that must be met is ______.
   A．ET0=1 B．EX0=1 C．EA=EX0=1 D．EA=ET0=1
(9) In order to make the interrupt request signal of timer T0 get the interrupt response of CPU, the condition that must be satisfied is ______.
   A．ET0=1 B．EX0=1 C．EA=EX0=1 D．EA=ET0= 1
(10) Use the timer T1 working mode 2 to count, and it is required to send an interrupt request to the CPU every 100 times, and the initial value of TH1 and TL1 should be ______.
   A．0x9c B．0x20 C．0x64 D．0xa0
(11) 80C51 MCU external interrupt 1 and external interrupt 0 trigger mode selection bit is ______.
   A．TR1 and TR0 B．IE1 and IE0 C．IT1 and IT0 D．TF1 and TF0
(12) When the interrupt response is not blocked, the minimum time required for the CPU to respond to an external interrupt request is ______ machine cycle.
   A．1 B．2 c. 3 D．8
(13) 80C51 microcontroller timer T0 overflow flag TF0, when the count is full after the CPU responds to the interrupt ______.
   A．Cleared by hardware B．Cleared by software C. Both software and hardware can be cleared D. Random state
(14) After the CPU responds to the interrupt, the correct sequence for the hardware to automatically perform the following operations is ______.
   ①Protect the breakpoint, that is, push the content of the program counter PC into the stack to save it.    ②Call the interrupt    function
   and start running    . cleared interrupt request flag



   A．①③②⑤④B．③②⑤④① C．③①②⑤④ D．③①⑤②④
(15) If 5 interrupt sources of the same priority of 80C51 send interrupt requests at the same time, the program counter PC will automatically load the ______ address when the CPU responds to the interrupt.
   A．000BH B．0003H C．0013H D．001BH
(16) The entry address of the interrupt service routine of the 80C51 single-chip microcomputer refers to ______.
   A．The address of the first sentence of the interrupt service routine B．The return address of the interrupt service routine
    C. Interrupt vector address D. Breakpoint address when the main program is called
(17) ______ in the following description about the definition format of the C51 interrupt function is incorrect.
   A．n is the interrupt number corresponding to the interrupt source, the value is 0~4
   B. m is the group number of the working register group, which is determined by RS0 and RS1 of PSW by default.
   C. Interrupt is a keyword of C51 and cannot be used as a variable name
   D. using is also a keyword of C51, which cannot be omitted
(18) ______ is correct in the following description of INT0.
   A．The interrupt trigger signal is input by the pin P3.0 of the microcontroller
   B. The interrupt trigger mode selection bit ET0 can realize the selection of level trigger mode or pulse trigger mode
   C. When the level is triggered, the high level can cause IE0 to be automatically set, and IE0 can be automatically cleared after the CPU responds to the interrupt
   . When the pulse is triggered, the falling edge causes IE0 to be automatically set, and IE0 can be automatically cleared after the CPU responds to the interrupt.
(19) The ______ in the following description about TX/RX is incorrect.
   A．Both the internal sending controller and receiving controller of the 51 single-chip microcomputer can send and receive serial data.
   B. If the data to be received is sent to the "receive SUBF" unit, the receiving controller can set the RI bit hardware to 1
   C. If the data in the "send SUBF" unit is sent out, the sending controller can set the TI bit hardware to 1.
   D. After the system responds to the interrupt, RI and TI will be automatically cleared to 0 by the hardware, without software intervention
(20) ______ in the following description of the interrupt control register is incorrect.
   A．The 80C51 has 4 interrupt-related control registers
   B. TCON is the serial port control register, the byte address is 98H, and it can be bit-addressed
   C. The IP register is an interrupt priority register, the byte address is B8H, and it can be bit-addressed
   D. IE is the interrupt enable register, the byte address is A8H, and it can be bit-addressed
(21) ______ in the following description about interrupt priority is incorrect.
   A．Each interrupt source of 80C51 has two interrupt priorities, namely high priority interrupt and low priority interrupt
   B. A low-priority interrupt function can be interrupted by a high-priority interrupt during execution
   C. When interrupts of the same priority are running, the interrupt with higher natural priority can interrupt the interrupt with lower natural priority
   . 51 After the MCU is reset, the initial IP value is 0, and the default is that all interrupts are low-level interrupts.

Chapter 6 Multiple Choice Questions

(1) The C51 command to make the 80C51 timer/counter T0 stop counting is ______.
A．IT0=0;B．TF0=0;C．IE0=0;D．TR0=0;
(2) When the timer T1 of the 80C51 single-chip microcomputer is used as a timing method, it is ______.
A．Timed by the internal clock frequency, one clock cycle plus 1 B. Timed by the internal clock frequency, one machine cycle plus 1
C. Timing by the external clock frequency, one clock cycle plus 1 D. Timed by the external clock frequency, one machine cycle plus 1
(3) When the timer T0 of the 80C51 single-chip microcomputer is used as a counting method, it is ______.
A．Timed by the internal clock frequency, one clock cycle plus 1 B. Timed by the internal clock frequency, one machine cycle plus 1
C. Counting by external counting pulses, one pulse plus 1 D. Counting by the external counting pulse, one machine cycle plus 1
(4) When the timer T1 of 80C51 is used as the counting mode, .
A．The external counting pulse is input by T1 pin) B. The external counting pulse is provided by the internal clock frequency
C. The external counting pulse is input by T0 (pin) D. The external counting pulse is input by any pin of P0 port
(5) when the timer T0 of 80C51 is used as a timing method .
A．Timed by the internal clock frequency, one clock cycle plus 1 B. Counting by external counting pulses, one machine cycle plus 1
C. The external counting pulse is timed by T0 (input timing D. It is timed by the internal clock frequency, and one machine cycle is added by 1.
(6) Set the frequency of the 80C51 crystal oscillator to 12MHz. If the working mode 1 of the timer T0 is used to generate 1ms timing, the initial value of T0 counting should be It is ______.
A. 0xfc18 B. 0xf830 C. 0xf448 D. 0xf060
(7) When the timer T1 of 80C51 is used as a timing mode and mode 1 is selected, the working mode control word is ______.
A．TCON=0x01;B．TCON=0x0H;C．TMOD=0x10;D．TMOD=0x50;
(8) When the timer T1 of 80C51 is used as a timing mode and mode 2 is selected, the working mode control word is ______.
A．TCON=0x60; B．TCON=0x02; C．TMOD=0x06; D．TMOD=0x20;
(9) When the timer T0 of 80C51 is used as a timing mode and mode 0 is selected, the initialization programming of C51 is ______.
A．TMOD=0x21;B．TMOD=0x32;C．TMOD=0x30;D．TMOD=0x22;
(10) When using 80C51 timer T0, if TR0 is allowed to start the counter, ______ in TMOD should be enabled.
A．GATE position 1B. C/T position 1 C．GATE bit is cleared D．Clear the C/T bit
(11) When using the timer T0 of 80C51, if INT0 is allowed to start the counter, the ______ in TMOD should be enabled.
A．GATE position 1B. C/T position 1 C．GATE bit is cleared D．The C/T bit is cleared
(12) The instruction to start timer 0 to start counting is to make the ______ of TCON.
A．TF0 position 1B. TR0 position 1 C. TF0 bit is cleared to 0D. TF1 bit is cleared to 0
(13) The C51 instruction to start timer 1 to start timing is ______.
A．TR0=0;B．TR1=0;C．TR0=1;D．TR1=1;
(14) The C51 command to stop counting of timer T0 of 80C51 is ______.
A．TR0=0;B．TR1=0;C．TR0=1;D．TR1=1;
(15) The C51 command to stop the timer T1 of 80C51 is ______.
A．TR0=0;B．TR1=0;C．TR0=1;D．TR1=1;
(16) The TMOD mode control register of the 80C51 microcontroller, where the GATE bit represents ______.
A．Gating bit B. Working mode definition bit C. Timing/counting function selection bit D．Operation control bit
(17) When 80C51 adopts counter T1 mode 1, it is required to generate an overflow flag if it is not counted up to 10 times, then the initial value of TH1 and TL1 is ______.
A．0xff, 0xf6B. 0xf6, 0xf6 C．0xf0, 0xf0D. 0xff, 0xf0H
(18) When 80C51 adopts T0 counting mode mode 1, the C51 command is ______.
A．TCON=0x01;B．TMOD=0x01;C．TCON=0x05;D．TMOD=0x05;
(19) Use 80C51 timer T0 for timing, and use mode 2, then it should ______.
A．Before starting T0, set the initial counting value to TH0, and set TL0 to 0, and then reset the initial counting value before each re-counting.
B. Before starting T0, put the initial counting value into TH0 and TL0, and then reset the initial counting value before each re-counting.
C. Before starting T0, put the counting initial value into TH0 and TL0, and then no longer put it into
D. Before starting T0, put the same counting initial value into TH0 and TL0, and then no longer put it into the
TMOD mode control register of the 80C51 single-chip microcomputer, where the C/T bit indicates ______.
A．Gating bit B. Working mode definition bit C. Timing/counting function selection bit D．run control bit
(21) The overflow flag TF1 of the 80C51 single-chip timer T1, when the count is full and overflows, if the query method is used instead of the interrupt method, then ______.
A．Should be cleared by hardware B．Should be cleared by software C. Should be set by software D.
(22) The overflow flag TF0 of the 80C51 microcontroller timer T0, when the count is full and overflow occurs, its value is ______ .
A．0B．0xff C．1D. Counting value
(23) The maximum counting value M of the timer/counter of the 80C51 single-chip microcomputer in working mode 1 is ______.
A．M=213=8192B．M=28=256C．M=24=16D．M=216=65536

Answers to Chapter 7 Multiple Choice Questions

(1) The C51 statement to read data from the serial port receiving buffer into the variable temp is ______.
   A．temp = SCON; B．temp = TCON; C．temp = DPTR; D．temp = SBUF;
(2) The characteristic of full-duplex communication is that the sending and receiving parties______.
   A．The role is fixed and cannot be interchanged B. The role can be changed but needs to be switched C. The two-way communication does not affect each other
   D. The mutual influence and mutual restriction
(3) Among the serial port working methods of 80C51, the one suitable for multi-computer communication is ______.
   A．Working mode 0 B. Working method 1 C. Working method 2D. Working mode 3
(4) The order in which the 80C51 serial port receives data is the following order______.
   ①After receiving a frame of data, the hardware automatically sets RI of SCON to 1. ②Clear RI by software. ③The
   received data is read out by SBUF. ④Set REN of SCON to 1, and the external data is input by RXD (P3.0)
   A．①②③④B．④①②③ C．④③①②D．③④①②
(5) The order in which the 80C51 serial port sends data is the following order______.
   ①The data to be sent is sent to SBUF ②The hardware automatically sets the TI of SCON to 1
   ③Serially send a frame of data through TXD (P3.1) ④Clear the TI of SCON by software
   A. ①③②④B．①②③④C．④③①② D．③④①②
(6) When 80C51 uses serial port working mode 0, ______.
   A．Data is serially input from RXD and serially output from TXD
   B．Data is serially output from RXD and serially input from TXD
   C. The data is serially input or output from RXD, and the synchronization signal is output from TXD
   . The data is serially input or output from TXD, and the synchronization signal is output from RXD
(7) When using the interface to transmit information, if a frame is used to represent a character, and each frame has a start bit, an end bit and several data bit, the transfer belongs to ______.
   A．Asynchronous serial transmission b. Asynchronous parallel transmission C. Synchronous serial transmission d. Synchronous parallel transmission
(8) The serial port working mode of 80C51 is ______ suitable for point-to-point communication.
   A．Working mode 0 B. Working method 1 C. Working method 2D. Working mode 3
(9) ______ in the description about the internal structure of the serial port of 80C51 is incorrect.
   A．There is a programmable full-duplex serial communication interface inside 51
    B. The serial interface of 51 can be used as a general asynchronous receiver/transmitter, or as a synchronous shift register
    C. Receive control register SCON
    D is provided in the serial port. The serial communication speed can be changed by setting the serial communication baud rate
(10) ______ in the description of the serial data buffer of 80C51 is incorrect.
   A．There are two data buffers SUBF in the serial port
    B. The two data buffers are physically independent and have different addresses
    C. SUBF hair can only write data, can not read data
    D. The SUBF receiver can only read data, but cannot send data
(11) ______ in the description of the function of the 80C51 serial port sending controller is incorrect.
   A．The first function is to convert the parallel data to be sent into serial data
    B. The second function is to automatically add start bits, programmable bits and stop bits to the serial data
    C.
    The third function is to automatically set the interrupt request flag TI to 1 after the data conversion is completed. The fourth function is to automatically clear the interrupt request flag TI after the interrupt is responded to
(12) ______ is incorrect in the following description of the function of the 80C51 serial port receiving controller.
   A．The first function is to convert the serial data from the RXD pin into parallel data
    B. The second function is to automatically filter out the start bit, programmable bit and stop bit in the serial data
    C. The third function is to automatically set the interrupt request flag RI to 1 after receiving
    . The fourth function is to automatically clear the interrupt request flag RI after the interrupt is responded to
(13) ______ in the following description of timer T1 in the process of 80C51 serial port transceiver is incorrect.
   A．The function of T1 is to generate the communication clock pulse for serial transceiver beat control, and it can also be replaced by T0
    . When sending data, the falling edge of the clock pulse corresponds to the shift output of the data
    C. When receiving data, the rising edge of the clock pulse corresponds to the data bit sampling
    D. The communication baud rate depends on the working mode of T1 and the initial counting value, and also depends on the setting value of PCON
(14) ______ in the following description of the integrated chip 74LS164 is incorrect.
   A．74LS164 is an 8-bit serial-in-parallel-out shift register
    B. The shift process of 74LS164 is realized by the working principle of D flip-flop
    C. After the 8 shifts, the output Q0 of the 74LS164 latches the highest bit of the data, and Q7 latches the lowest bit
    D．The combination of 74LS164 and 80C51 serial port mode 0 can realize the expansion function of the parallel output port of the single chip microcomputer
(15) Compared with serial port mode 0, the following changes in serial port mode 1 are ______ wrong.
   A．The communication clock baud rate is variable and can be set to different rates by software
   B. The data frame consists of 11 bits, including 1 start bit + 8 data bits + 1 parity bit + 1 stop bit
   C. The sending data is output by the TXD pin, and the receiving data is input by the RXD pin
   D. Mode 1 can realize asynchronous serial communication, while mode 0 can only realize serial-to-parallel conversion
(16) Compared with serial port mode 1, the following changes in serial port mode 2 are ______ wrong.
   A．The baud rate of the communication clock is fixed, and its value is equal to the frequency of the crystal oscillator
   B. The data frame consists of 11 bits, including 1 start bit + 8 data bits + 1 programmable bit + 1 stop bit
   C. TI can be automatically set to 1 after sending, but the state of RI after receiving is determined jointly by SM2 and RB8
   . The parity check in the process of asynchronous communication can be realized
(17) ______ in the following description about serial port mode 3 is wrong.
   A．The baud rate of mode 3 is variable and can be set to different rates by software
   B. The data frame consists of 11 bits, including 1 start bit + 8 data bits + 1 programmable bit + 1 stop bit
   C. Mode 3 is mainly used in occasions requiring error checking or master-slave system communication
   D. Both TI and RI can be automatically set to 1 by hardware after the sending and receiving process is over
(18) ______ is wrong in the following description of the serial master-slave communication system.
   A．The master-slave communication system consists of a master and several slaves
   B．Each slave must have the same communication address
   C. The RXD end of the slave machine is connected to the TXD end of the master machine in parallel, and the TXD end of the slave machine is connected to the RXD end of the master machine in parallel.
   D. Information cannot be directly transmitted between slaves, and can only be realized indirectly through the master
(19) ______ is wrong in the following description of the working principle of multi-machine serial asynchronous communication.
   A．In the multi-machine asynchronous communication system, each machine should be set to the same baud rate when initializing
   B. All slaves should be set to serial port mode 2 or mode 3, SM2=REN=1, and serial port interrupts are prohibited
   C. The master first sends an address message containing TB8=1, all slaves can verify this address in the interrupt response, but only the target slave changes SM2 to 0
   D. The host then sends data or command information containing TB8=0, at this time only the target slave can respond to the interrupt and receive this information
(20) Assuming that the asynchronous serial interface transmits 6000 characters per minute in mode 1, then its baud The rate should be ______.
   A．800 B. 900 C. 1000 D. 1100
(21) In a communication system using serial port mode 1, it is known that fosc=6MHz, baud rate=2400, SMOD=1, then the counting of timer T1 in mode 2 The initial value should be ______.
   A．0xe6 B. 0xf3 C. 0x1fe6 D. 0xffe6
(22) The indicator of the serial communication rate is the baud rate, and the dimension of the baud rate is ______.
    A. Character/second B. Bit/second C. Frame/second D. Frame/minute

Answers to Chapter 8 Multiple Choice Questions

(1) Among the following types of chips, it is a digital-to-analog converter.
   A．74LS273 B．ADC0809 C．74LS373 D．DAC0832
(2) Among the chips of the following models, it is an analog-to-digital converter.
   A．74LS273 B．ADC0809 C．74LS373 D．DAC0832
(3) Among the chips of the following models, it is a programmable parallel I/O port expansion chip.
   A．74LS273 B．8255A C．74LS373 D．DAC0832
(4) If the address of the control register of the 8255A chip is 0xe003, the address of its A port and B port is .
   A．0xe001, 0xe002 B．0xe000, 0xe001 C．0xe004, 0xe005 D．0x0a, 0x0b
(5) When 80C51 uses the serial interface to expand the parallel I/O port, the working mode of the serial interface should be selected .
   A. Way 0 B. Way 1 C. Way 2 D. Way 3
(6) ______ in the following description about the bus is wrong.
   A．The wire that can transmit data, address and control three types of information at the same time is called the system bus
   B. Data can be transmitted from the CPU to the memory or I/O port, and can also be transmitted from these components to the CPU, so the data bus is bidirectional
   C. Addresses can only be passed from the CPU to memory or I/O ports, so the address bus is unidirectional
   D. The direction of control information is determined by the specific control signal, so the control bus is generally bidirectional
(7) ______ in the following description about the off-chip bus structure of the 51 single-chip microcomputer is wrong.
   A．The data bus and address bus adopt the multiplexing P0 port scheme
   B. The 8-bit data bus is composed of P0 port
   C. The 16-bit address bus is composed of P0 and P1 ports
   D. The control bus is composed of P3 port and related pins
(8) ______ is wrong in the following description about the principle of the address latch interface chip 74373.
   A．74373 consists of 8 D flip-flops triggered by negative edges and 8 tri-state gate circuits controlled by negative logic
   B. After applying a negative pulse trigger signal at the 74373LE terminal, the 8 D flip-flops can complete a "turn on-latch-isolate" operation. C. The
   ALE pin of 80C51 is specially designed for address latch, and its output pulse Can be used as a trigger signal for 74373
   D. After executing the off-chip RAM write command, the output port of 74373 is the lower 8-bit address, and the input port is 8-bit data
(9) ______ in the following description about the I/O port expansion port is wrong.
   A．51 The I/O expansion port of the single-chip microcomputer occupies the address space of the off-chip RAM
   B. Access to the I/O expansion port can only be done through the off-chip bus
   C. When using the MOVX instruction to read the data of the I/O expansion port, the CPU sequence contains /RD negative pulse signal
   D. When using the C51 pointer to read the data of the I/O expansion port, there is no /RD negative pulse signal in the CPU timing sequence
(10) ______ is wrong in the following description of the integrated expansion chip 74273.
   A．74273 is composed of 8 D flip-flops, which can realize the expansion function of 8-bit parallel input interface
   B．The trigger signal at the clock terminal can first latch the data at the input terminal to the output terminal, and then generate isolation between the two ends
   C. When using the bus mode to expand the output port, the timing signal of the 80C51 write port and the address strobe signal of the port should be used as the trigger signal of the 74273
   D. The practice of Example 1 in this chapter is to connect the /WR pin of 80C51 and a certain address line pin to the clock terminal CLK of 74273 through an OR gate (
11) Assume that the /WR pin of 80C51 and the P2.5 pin are connected in parallel On an OR gate input terminal, the OR gate output terminal is connected to the clock terminal of 74273. If 74273 can be triggered after 80C51 executes a write port command, then the address of the port (assuming that the irrelevant address bits are all 1) is .
   A, 0xfeff B, 0xdfff C, 0x7fff D, 0xefff
(12) ______ in the following description about integrated expansion chip 74244 is wrong.
   A．74244 is composed of 8 three-state gate circuits, which can realize the expansion function of two 4-bit parallel input interfaces
   . When the strobe signal is high, the three-state gate is turned on, otherwise the three-state gate is turned off, and the input and output are in a high-impedance state
   C. When using the bus mode to expand the input port, the timing signal of the 80C51 read port and the address strobe signal of the port should be used as the strobe signal of the 74244
   D. The practice of Example 2 in this chapter is to connect the /RD pin of 80C51 and a certain address line pin to the strobe terminal /OE of 74244 through an OR gate (
13) When 80C51 is connected with a programmable parallel interface chip 8255A, it needs to occupy ______Extended port address.
   A.1 B.2 C.3 D.4
(14) Use 8255A to expand the ______8-bit I/O port.
   A. 1 B. 2 C. 3 D. 4
(15) If you want to set the A port and the upper C port of the 8255A as the basic input mode, and the B port and the lower C port as the basic output mode, then the control word Should be______.
   A．0x83 B．0x88 C．0x98 D．0x99
(16) When 8255A and 80C51 adopt a typical bus connection mode, if the /CS, A1 and A0 pins of 8255A are respectively connected to P2.2, P2.1 and P2.0 pins of 80C51, the control port address of 8255A (assuming irrelevant The address bits are all 1) should be ______.
   A．0xf9ff B．0xf8ff C．0xfbff D．0xfaff
(17) ______ in the following description about DAC0832 is wrong.
   A．DAC0832 is an 8-bit voltage output digital-to-analog converter
   B. It consists of an 8-bit input latch, an 8-bit DAC register and an 8-bit D/A converter
   C. Its digital-to-analog conversion result depends on the chip reference voltage VREF, the digital quantity to be converted and the internal resistance network
   D. DAC0832 can choose 3 working modes: straight-through, single-buffering and double-buffering
(18) The 5 external control pins of DAC0832 determine its working mode. When LE=Vcc, /CS=/WR1=/WR2=/XFER are connected in parallel GND, it works by ______.
   A．Straight through B. Single buffer mode C. Double buffer mode D. Wrong wiring status
(19) After DAC0832 is combined with an inverting operational amplifier, the digital quantity can be directly converted into a voltage quantity output. If the reference voltage is 5V, when the digital quantity changes by one LSB, the output voltage will change by about ______.
   A．-100mV B．-50mV C．-30mV D．-20mV
(20) The ADC0809 chip is an n-bit AD converter with m analog inputs, m and n are ______.
   A．8,8 B．8, 9 c. 8, 16 D. 1, 8
(21) ______ is wrong in the following description about the working principle of the analog-to-digital converter ADC0809.
   A．ADC0809 is composed of core units such as voltage comparator, D/A converter and latch buffer
   B. When the voltage to be converted is sent to the voltage comparator, a positive pulse on the START pin can start the AD conversion process
   C. The conversion process is based on correcting the digital conversion value bit by bit starting from the low bit, and the conversion ends after the highest bit is corrected.
   D. After the conversion is completed, the digital conversion value is output by the latch buffer, and the EOC pin sends a negative pulse to indicate the end of the conversion. (
22) If the ADDA, ADDB and ADDC pins of the ADC0809 are respectively connected to GND, VCC and VCC, the selected multi-channel The analog quantity is the ______ channel.
   A．0 B．3 C．5 D．7
(23) The ______ in the following description of the working timing of the analog-to-digital converter ADC0809 is correct.
   ① The EOC pin changes from high level to low level and maintains until the end of the conversion.
   ② After the conversion, the EOC pin changes from low level to high level.
   ③ A positive pulse on the START pin makes the AD conversion start.
   ④ OE After the pin becomes high level, the conversion result is latched to the output terminal, and OE becomes low level after the CPU reads the data.
   A. ①③②④B．③①②④ C．①④③② D．③④①②
(24) If you want to realize the switch control function of a 12V 100mA DC motor through the P1 port of 80C51, ______ is reasonable in the following power drive interface scheme.
   A．Tri-state gate buffer 74LS244 B. OC gate circuit 7407
   C. Darlington driver ULN2003 D．DC Electromagnetic Relay

Chapter 9 Multiple Choice Questions Answers

(1) ______ in the following description about the minimum system of 80C51 single-chip microcomputer is wrong.
   A．It is a basic application system composed of single-chip microcomputer, clock circuit, reset circuit and power supply
   B. It does not have a timer interrupt function
   C. It does not have analog-to-digital or digital-to-analog conversion functions
   D. It does not have the function of switching power drive
(2) ______ is correct in the following description about the general development process of the single-chip microcomputer application system.
   ① Carry out overall demonstration on the basis of feasibility analysis
   ② Carry out functional program modular design and allocate system resources after the overall software structure design
   ③ Carry out system function allocation, determine the division of labor and mutual relationship between software and hardware
   ④ In circuit schematic design Carry out hardware development, circuit debugging and PCB plate-making on the basis of
   ⑤ use general-purpose development device or software simulation development system for online debugging of software and hardware
   A. ①③④②⑤B．①②③④⑤ C．①④③②⑤D．③④①②⑤
(3) ______ is correct in the following sequence description of using Proteus to develop a single-chip microcomputer system.
   ① Create a real single-chip system circuit, run it, debug it until it succeeds
   ② Use the object code for real-time interaction and co-simulation
   ③ Carry out circuit drawing design, select components, connect circuits and electrical appliances, etc.
   ④ Source program design, programming, assembly compilation, debugging , Generate object code file
   A. ①③②④B．①②③④C．①④③② D．③④②①
(4) ______ is wrong in the following description about the "watchdog" technology.
   A．Its significance is that it can realize self-diagnosis and restore the system when the program "runs away"
   B. The basic principle is that if the "feed the dog" rule is broken, it will guide the system to reset and start the program again
   C. The pulse used for "feeding the dog" can come from either the hardware circuit timer or the internal timer of the single-chip microcomputer
   D. After using the "watchdog" technology, the system anti-jamming problem can be completely solved
(5) According to the application examples of intelligent instruments in Chapter 9, ______ in the following description of hardware design is wrong.
   A．A display scheme based on the dynamic display principle of common cathode digital tubes is adopted
   B. A digital tube segment code power drive scheme based on an open collector gate (OC) is adopted
   C. The key interface scheme based on the serial port expansion method is adopted
   D. The analog-to-digital converter interface scheme based on the general-purpose I/O port is adopted
(6) According to the application examples of intelligent instruments in this chapter, ______ in the following description of software design is wrong.
   A．The software system is composed of two main functional modules - control module and menu module
   B. The idea of ​​making a long time-consuming function into a short time-consuming function is to decompose the long time-consuming function into many short functions
   C. The closed state of the button is divided into two stages of "pressing the button" and "lifting the button" for detection
   D. The serial port output function adopts the mixed programming of assembly language and C51 language
(7) The ______ in the following description of the working sequence of the serial A/D converter MAX1241 is correct.
   ① Enable the chip select signal /CS first, and keep the clock terminal at low level to start AD conversion
   ② Continuously send 13 shift pulses to output the converted data serially
   ③ The shift pulse of the SCLK pin The falling edge corresponds to bit data appearing on the DOUT pin
   ④ After the AD conversion is completed, the level of the pin DOUT changes from low to high
   A. ①③②④B．①②③④ C.①④③② D．③④①②
(8) ______ is wrong in the following description of the key points of programming in Example 1 of this chapter.
   A．The clock pulse is effective on the falling edge, so at least 13 pulses are required to complete the shift of 12 bits of data
   B. The function of the statement result|=dout is to assemble bit data into parallel data
   C. The function of the statement pos=(pos>>1)|0x80 is to refresh the segment code of the dynamic display digital tube
   D．The ending moment of AD conversion in this example is realized by monitoring the DOUT pin level and then calling the interrupt function
(9) The following description of the serial D/A converter LTC145X working sequence is ______ correct.
   ① Pull the chip select terminal /CS/LD low, and load the MSB bit data at the DIN terminal.
   ② After continuously sending 12 shift pulses, all the 12bit data to be converted are sent to the internal DAC register.
   ③ CLK terminal sends out a shift pulse. Bit data is written into the shift register
   ④ After the DA conversion is completed, the chip select terminal /CS/LD is pulled high to prepare for the next round of conversion
   A. ①③②④B．①②③④C．①④③② D．③①②④
(10) ______ is wrong in the following description of the key points of programming in Example 2 of this chapter.
   A．According to the timing requirements, as long as the bit variable cs sends a positive pulse, the D/A conversion process can be ended.
   B. The function of the statement din=(v>>i)&0x01 is to disassemble parallel data into bit data
   C. Statement value=2047+2047 sin((float)num/180The role of float in PI) is to convert the integer variable num to a floating point number to meet the floating point number requirement of the sine function sin()
   D. The variable v to be converted should be able to store 12-bit data, so it needs to be defined as int type
(11) According to the textbook Figure 9.29, ______ in the following description of I2C communication timing is wrong.
   A．During the high level of SCL, the transition sequence of SDA from high to low will start the communication process
   B. The transmitter pulls SDA low at the 9th cycle of SCL after sending a byte, and the receiver feeds back a response signal
   C. Only when SCL is high, the level state of SDA is allowed to change
   D. When SCL is high level, the transition sequence of SDA from low to high will terminate the communication process
(12) In a serial E2PROM memory circuit, if the addressing information SLA=1010011xB of AT24CXX is known, then the device’s Chip select address A2, A1, A0 should be ______.
   A．1, 0, 1 B．0, 1, 1 C. 1, 0, 0 D．0, 0,
1 (13) If it is known that the device type identifier of the E2PROM memory AT24C01A is 1010B, and the A0, A1, and A2 pins are respectively connected to Vcc, Vcc and GND, then the addressing information SLA of the device should be ______ .
   A．1101010xB B．1010011xB C．1010110xB D．0111010xB
(14) ______ is wrong in the following description of programming points in Example 3 of this chapter.
   A．80C51 has no I2C interface, and the communication with 24C01 uses the software simulation method of I2C timing
   B. The I2C timing simulation in this example is written in assembly language for better real-time reading and writing
   C．According to the schematic diagram of the circuit, the chip address of the 24C01 device is 111B
   D. The function of &count in the statement write_e2prom(E2PROM_ADDR,(unsigned char)&count,1) is to read the address of the count value variable count
(15) ______ in the following description of LM1602 is wrong.
   A．It is a character type liquid crystal display module with 16*2 display bits
   B. Each display bit has a RAM unit (display buffer) corresponding to it
   C. The display buffer has the characteristic that it can only be written but not read
   D. The timing of control signals for writing instructions into registers and writing data into buffers is different
(16) ______ is wrong in the following description of programming points in Example 4 of this chapter.
   A．Initialization tasks include clearing the screen, setting the display format, displaying the cursor and making it blink, and moving the cursor one bit to the right in turns
   B. The management of the display is to send the command code by calling the write command function
   . The character to be displayed is the ASCII code data sent out by calling the write data function
   D. The structure of the write command function and the write data function is the same, the only difference is that the sending object is different
(17) ______ is wrong in the description of the working characteristics of the serial calendar clock chip DS1302.
   A．It can time the year, month, day, week, hour, minute and second in real time, and has the function of leap year compensation
   B. There is a 32-byte RAM area inside for storing temporary data
   C. Synchronous communication with single-chip microcomputer using three-wire interface
   D.
The ______ in the following description of the working timing of the serial calendar clock chip DS1302 with a wide voltage range of 2.0-5.5 volts (18) is wrong.
   A．The transmission of data or commands is allowed only when the reset pin CE is set to a high level
   . All read and write operations are guided by the command byte, followed by the data byte
   C. The rising edge of the shift pulse corresponds to the signal enable of the command and data byte write operation
   D. The falling edge of the shift pulse corresponds to the signal enable of the command and address byte read operation
(19) ______ is wrong in the following description of the programming points in Example 5 of this chapter.
   A．The basic flow of the main function is to repeatedly read the data in the RTC register of DS1302 and send it to LM1602 for display
   . B．The shift pulse in the read and write DS1302 functions is generated by software
   C. The byte data to be sent is transformed into bit data by using the circular left shift operation of the accumulator
   D. The calendar data in compressed BCD format is split into tens and ones data by dividing by 16 and modulo 16.
(20) Among the following interface chips, the one with the function of serial input and output shift register is ______.
   A．MAX124X B．LTC145X C.AT24CXX D.74LS164