Interface transmission timing
Frame interface framing mode :
Frame Interface Timing
simple transfer
data transfer suspended
Clock Compensated Data Transmission
The clock compensation sequence is sent when the display core automatically interrupts the data transfer. Data Transfer Pause Clock Compensation
data reception
Transmission efficiency of frame transmission mode
There are two factors that affect the transmission efficiency of the Aurora 64B/66B core:
1. The size of the frame.
2. A data invalidation request from the gearbox occurs once every 32 user_clk(txusrclk2) cycles.
The gearbox in the GTX and GTH transceivers requires periodic pauses to account for clock divider ratios and 64B/66B encoding. This manifests itself as backpressure in the AXI4-Stream interface, where user data needs to be stopped for one cycle after every 32 cycles (as shown). The s_axi_tx_tready signal in the user interface from the Aurora 64B/66B core is deasserted in one cycle, once every 32 cycles. The pause period is used to compensate for gearbox's 64B/66B encoding.
streaming data interface
Streaming Interface Timing
Send timing
Receive Timing
Debugging experience
PMA_INIT is a synchronous reset signal, which needs to be pulled down after ref_clk arrives to reset. The following method can be used. After the differential ref_clkp/ref_clkn passes through IBUFDS_GTE2, the output clock ref_clk is provided to the aurora IP core, and a PLL is instantiated at the same time, and ref_clk passes through the PLL Afterwards, init_clk and drp_clk are generated and provided to the aurora IP core, and the locked signal is generated at the same time, which is used as the IP core reset signal after inversion. This guarantees a synchronous reset.
For the programming crystal oscillator clock of the development board, the high and low levels of the DIP switch are dialed according to the circuit diagram. "On" means that the switch is turned on, and it does not mean that it is set to 1. According to the circuit diagram, after dialing to "on" in the figure below, the circuit and GND Conduction, at this time, the low level is provided to the programming crystal oscillator.
For the TX side, an asynchronous FIFO can be connected, which solves the problem of crossing the clock domain from the data source to the aurora IP core tx_data,
Also for RX, connect an asynchronous FIFO
During verification, lane_up and channel_up represent link establishment and channel establishment, and gt_pll_lock and gt_qpllock_out represent PLL lock. This signal can verify whether the clock is input and the frequency is correct during the debugging process. A large part of the successful debugging is the input clock.
The following figure is a simulation diagram of streaming data. When tx_tready and tx_tvaild are pulled high at the same time, the data is effectively transmitted. When rx_tavild is pulled high, it means that the data received by RX is valid.
tx_tready is pulled down every 256ns, and the cycle of clk_user is 8ns, indicating that the IP core performs clock compensation every 32 clock cycles.
For the input of tx_fifo and the output of rx_fifo, the write clock rate of tx_fifo and the read clock rate of rx_fifo are less than clk_user, so data can always be written to tx_fifo, and data is always read from rx_fifo.
