In the past few years, SoC has almost become the crown jewel of the smart car industry. Automotive chips are rapidly shifting from general-purpose, decentralized single-function chips (MCU) to integrated multi-functional SoC (System on Chip) chips.
For example, in the field of smart cockpits, CPU computing power is used to improve task processing capabilities, GPU computing power is also required to process unstructured data such as videos, and efficient AI computing power is used to meet the requirements of intelligent interactive experience, thereby improving the human-computer interaction experience . These different IP cores form a powerful SoC.
In fact, in the fields of high-performance computing, consumer electronics, communications and automotive applications, SoC has always been a major form of chip products. At the same time, chip design companies will combine different types of IP according to different system specifications and application scenarios, and match them with self-developed custom IP.
Behind the SoC, different manufacturing processes determine the upper limit of hardware performance to a certain extent. For example, compared with the 10nm process, the performance of the 7nm process is improved by 20%, the energy efficiency is increased by 40%, and the transistor density is increased by 1.6 times, achieving a double improvement in performance and energy efficiency.
However, as the advanced process iterates to 5nm and 3nm, Moore's Law (the number of transistors per square inch will double every 18 to 24 months) gradually slows down, and the development cost and difficulty of advanced processes increase.
At present, the consensus in the semiconductor industry is that tape-out costs for advanced manufacturing processes are getting higher and higher, and the success rate of tape-out is getting lower and lower; at the same time, the yield rate of chips has also begun to drop sharply. Compared with the mobile phone track, the automotive industry is in a period of accelerated improvement of intelligence, and the performance requirements for chips are infinitely magnified.
In addition, the trend of self-developed chips by car companies represented by Tesla is prevalent, and different car companies still have scruples about the homogenization of computing platforms. For example, in the cockpit field, Qualcomm's near-monopoly structure has also made more car companies and chip manufacturers think about alternatives.
On the one hand, for chip manufacturers, it is a strategic choice to continue to choose single-chip, more advanced process technology, or choose the Chipet (small chip high-speed interconnection) solution. At present, the latter is becoming the mainstream trend.
To give a simple example, under Chiplet's system-level architecture design, through advanced packaging technologies such as 2.5D/3D stacking, chips manufactured using a 10nm process can reach the integration level of a 7nm chip. Much less investment than 7nm chips.
In addition, modular chips can reduce repeated design and verification links, reduce chip design complexity and R&D costs, and speed up product iteration. At the same time, reducing the dependence on advanced manufacturing processes is also a cost reduction strategy for the automotive application market.
As we all know, Tesla took the lead in launching AMD's cockpit computing platform solution (Ryzen APU and GPU based on AMD RDNA 2 architecture) in the world. The latter is the vanguard of Chiplet technology application.
For example, on AMD's Ryzen 3000 series CPU, every 4 CPU cores form a CCX, and two CCXs form a CCD—that is, a die/chiplet. Multiple CCDs, plus I/O die, constitute a complete chip.
Last year, AMD officially released a new generation of flagship GPU using the RDNA 3 architecture. This is the first time the company has adopted Chiplet technology in GPU products. It has as many as 58 billion transistors, a 54% increase in performance per watt, and provides up to 61TFLOP computing power.
And that's just the first step.
According to the plan, AMD will seek products that are more in line with customer preferences in terms of chip design. For example, based on Chiplet technology, customers can flexibly configure third-party IP (based on different processes). In particular, the demand for car intelligence continues to be released, and the model of heterogeneous integration (for example, the coexistence of X86, Arm, and RISC-V) may become the mainstream of the market in the future.
Seeing this opportunity, there is also Nvidia. The company's previously launched NVIDIA® NVLink®-C2C is also an ultra-high-speed chip-to-chip, die-to-die interconnection technology that supports the realization of custom dies and NVIDIA GPUs, CPUs, DPUs, NICs and SOCs Consistent interconnection.
With advanced packaging technology, NVLink-C2C interconnect links can be up to 25 times more energy efficient and 90 times more area efficient than PCIe Gen 5, enabling consistent interconnect bandwidths of 900GB per second or higher.
"In response to the slowdown of Moore's Law, it is necessary to develop small chips and heterogeneous computing." From the perspective of Nvidia, this chip giant, which has already taken the lead in the autonomous driving track, also covets a huge market. domain market.
For example, the “DRIVE Thor” officially unveiled by Nvidia last year has a single chip with a computing power of 2000 TFLOPS, and supports multi-domain computing through the NVLink-C2C interconnection of multiple chips to separate key safety functions such as autonomous driving. and information and entertainment functions.
Interestingly, the latest generation of DRIVE Thor, which will be mass-produced in 2024 and put on the car in 2025, uses a 5nm process, which has already started mass production as early as 2020. The marriage between Nvidia and MediaTek has further pushed Chiplet to the center of the stage.
On May 29, Nvidia and MediaTek announced that they will jointly provide solutions for a new generation of smart cars. The first chip of the cooperation is locked in the smart cockpit, which is expected to be released in 2025 and put into mass production from 2026 to 2027.
In terms of this chip design, MediaTek will develop an SoC that integrates NVIDIA GPU chips, equipped with NVIDIA AI and graphics computing IP, and realizes high-speed interconnection between the main chip and GPU chips based on chiplets.
From the perspective of car companies, on the one hand, customization needs are emerging, and more and more car companies have begun to interact with upstream chip design companies to put forward their own clear needs. But the latter is more to assist car companies to accelerate system development by providing tool chains and building a Tier1 ecological partner circle.
At the same time, not all chip manufacturers can share the high research and development costs of advanced process technology chips through multiple large-scale application markets like Nvidia and Qualcomm.
On the other hand, combined with the rapid growth of intelligent cockpit and intelligent driving assistance computing power, driven by the pre-buried computing power and the continuous upgrade of OTA in the life cycle, the market urgently needs large computing power, cost-effective, flexible and scalable vehicle-mounted chips platform.
In the view of Xinli Intelligent, the emergence of Chiplet technology also means that it is possible to achieve a leap in computing power through architectural innovation. In the view of Gaogong Intelligent Automobile Research Institute, due to the differences in product positioning of different car companies, the performance requirements for chips are actually not the same.
However, the reality is that the chips available on the market are all standardized products. Car companies can only carry out differentiated development at the level of function definition and software algorithms. At the same time, the product roadmap must be consistent with that of chip manufacturers. In addition, in order to get the first launch of the latest generation of products, car companies often need to pay a lot of money.
This gives Chiplet technology and new opportunities for suppliers of in-vehicle smart chip platforms like Xinli Smart. Under this brand-new chip development model, Core Smart can combine chips based on different quantities and types of chips to meet the diverse needs of the market and different customers for chip computing power.
On June 15th, the Die-to-Die Interconnect IP independently developed by Xinli Intelligent obtained the ISO 26262 ASIL-D Ready certification, which means that the company's IP meets the highest functional safety requirements and can be applied in applications with the highest safety requirements. car scene.
One of the cores of Chiplet technology is how to realize high-speed interconnection between small chips, so as to realize the combination of multi-chip computing power under large bandwidth, and complete the efficient integration of heterogeneous complex high-performance SoCs.
At the same time, the electronic architecture of smart cars has evolved from distributed ECUs to centralized multi-domain controllers, and then to the future central computing platform (integrated cabin and driving). Chiplet technology has unique advantages.
At present, there are mainly three types of central computing solutions. One is SoCs with super-large computing power like NVIDIA Thor and Qualcomm Flex; the other is the combination of SoCs from different manufacturers, such as the cockpit SoC of manufacturer A + the smart driving of manufacturer B. SoC+C manufacturers' high-performance MCU; the third is the Chiplet technology solution.
One of the characteristics of the central computing architecture is uncertainty. Since the functions to be implemented by the platform are very complex, the integration level is constantly improving, which means that general-purpose chips are not enough to carry the definition of the needs of different car companies.
In the eyes of some industry insiders, for the automotive industry, Chiplets are a way to customize automotive SoCs. Most importantly, this approach allows automakers to regain architectural control and determine how computing platforms need to scale.
In terms of cost, taking AMD as an example, through the chiplet design idea, in addition to reducing the manufacturing cost by 40%, it can also sell server chips more flexibly, add and remove small chips as needed, and can target different functional options. Formulate price ranges for different chips.