2024考研408-计算机组成原理第二章-数据的表示学习笔记

foreword

Currently preparing for the 24 postgraduate entrance examination, the knowledge points learned and sorted out in 24 computer 408 are now summarized.

Blogger blog article directory index: blog directory index (continuously updated)

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1. Number system and coding

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1.1, carry counting system

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1.1.1. Counting method (the oldest counting method, decimal counting, r-ary counting)

The oldest counting method : Numbers represented by basic characters at the beginning have a defect that when we want to represent larger numbers, we need to construct larger characters, such as 10000, 100,000 and so on, this creates disadvantages.

• Among them, MDCCCLXXXVIII: means 1 1000 + 1 500 + 3 100..., and finally get this number through the idea of ​​addition.

Decimal notation :

位权·: The weight to represent according to the position of the corresponding number.

• Humans have 10 fingers, and they can add ten to one, which is more in line with the laws of human beings.

Promotion: r-ary notation

Hexadecimal: time

Computers usually use binary, octal, and hexadecimal. Different r systems need to add 1 every r.

基数: The number of different symbols used by each digital bit, the base of the r system is r.

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1.1.2, base conversion

① Convert arbitrary base to decimal

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②Binary to octal, hexadecimal

③Octal, hexadecimal to binary

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④ Decimal to arbitrary base (including integers, decimals, patchwork method)

For the processing of the decimal integer part: continuously obtain the number of digits through division

For decimal fraction processing:

Decimal to binary (patchwork method)

For conversion from decimal to octal or others, you can first convert to binary, then convert binary to the corresponding r-ary: as follows with the help of the above example and continue down, the final octal number obtained is 1025.1

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1.1.3. Common writing methods of various bases

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1.1.4, truth value and machine number

Knowledge review and important test points

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1.2, BCD code

1.2.1. Understanding BCD code

Four bits correspond to a decimal digit

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1.2.2. Know the encoding method of BCD: 8421 code (authorized code)

The encoding method of the first BCD code is: 8421, that is, every 4 digits represent a number

How to perform addition calculation for 8421 ?

①Hand calculation method: first use decimal to add to the result, and then convert to 8421 representation.

②Computer method:

Steps : ① First, perform binary calculation directly. ② Judging whether it is in 0-9 and defined in 1010-1111, if it is in direct expression, if it is not in +6. ③ The obtained result is represented by four bits in 8421 mode and corresponds to one bit.

Example For the case of 9+9 : the binary value of 18 is 10010. In fact, the whole has exceeded 1010-1111, so +6 is also required. At this time, the correction is 11000, which is 18.

Note: If the addition result is within the legal range, no correction is required.

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1.2.3, the remaining three yards (unauthorized code)

The remaining three yards refer to +3 on the 8421 yard to get a new mapping scheme.

In the 8421 code, each bit has a fixed weight, and the four bits represented are 8, 4, 2, and 1 respectively; in the remaining three codes, each bit has no fixed weight.

• 8421 is called the right code, and the remaining 3 yards are called the non-right code.

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1.2.4, 2421 yards

It is also represented by 4 bits, and the weights are 2 4 2 1 from left to right:

In order to avoid ambiguity, for example, 5 can also be represented by 0101 or 1011. At this time, a regulation is made for the 2421 code.

Convention: the first digit in 0-4 is 0, and the first digit in 5-9 is 1 ! ! !

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Knowledge review and important test points

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1.3, unsigned integer

Applications of unsigned integers in computers:

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1.3.1. Unsigned integers are represented inside the computer

The explanations are introduced according to the word length of 8 bits. At present, the machine word length of the general system is 64 bits or 32 bits.

Unsigned does not contain signed bits in binary, and 0s can be added if there are not enough 8 bits:

If the size of the true value exceeds 8 bits in binary, only the lower 8 bits will be kept in the register, and the extra bits will be omitted.

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1.3.2. Addition of unsigned integers

Add directly from the low bit to the high bit:

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1.3.3. Subtraction of unsigned integers

Subtraction: Turn subtraction into an addition operation.

Steps: ① The subtrahend remains unchanged, and all subtrahends are reversed + 1. ② Then calculate the binary number according to the addition operation.

Example: A=99, B=9, AB=90

A = 01100011
B = 00001001

①被减数不变 A = 01100011，减数全部取反+1 => 11110111
②加法运算
  01100011
+ 11110111
-----------
 101011010  => 90

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Review of Knowledge Points

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1.4. Representation and operation with signs (including original/reverse/complement)

For the same number, different original inverse complement representations can be used in the computer:

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Knowledge supplement (original, reverse, complement conversion, original code to complement quick method)

Positive number: the original negation remains unchanged.

Negative number: the inverse code is the inverse of the positive number, and the complement code is the inverse code +1.

• The above negative number conversion is the process of machine conversion!

A quick way to convert the original code of negative numbers to complement code : hand calculation is highly recommended

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1.4.1. Representation of signed integers (original code)

Also use the machine word length of 8 bits for demonstration!

The original code sign bit indicates :

If the machine word length is not specified, for x=-19, it can be expressed as [x] _original =1,10011

• Sign bit with a comma!

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1.4.2, the addition and subtraction of the original code

The addition and subtraction of the original code : if the original bitwise addition and subtraction is used, the final result will be wrong, and complex hardware circuits need to be designed to handle it

In fact, the complement code method can be used to carry out the operation!

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1.4.3, Complementary addition operation

Addition in two's complement: the rules for addition are the same as before

Example 1: Positive number + negative number, the final complement needs to be converted to the original code first to get its result value:

Example 2: Negative + Negative

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1.4.4. Complementary subtraction operation

How to implement the subtraction operation of complement code: in one sentence, [A] _complement - [B] _complement = [A] _complement + [-B] _complement

Example 1:

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Review and summary of knowledge points

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1.5. Comparison of original/inverse/complement code characteristics

Here is a little trick : To judge whether overflow, we can manually calculate their combined value first, if it exceeds the range of the corresponding code, then it means overflow.

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1.6, frame shift

1.6.1. Understanding frame shifting

How to get frameshift? The code shift can be obtained by inverting the sign bit on the basis of complement code.

The frame shift can only represent integers, but cannot represent decimals. There is only one representation for the true value 0, and its representation range is consistent with the complement!

If it is interpreted as an unsigned integer, the code shift is just 0-255 at this time.

Codeshift application : generally used for exponents of floating-point numbers.

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1.6.2. Use several codes to represent integers (new code shift part)

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1.6.3. Summary of basic characteristics of various codes (including frame shifting)

The comparison of various codes includes frame shifting:

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1.7, fixed-point integer (signed integer), decimal

1.7.1. Representation of fixed-point decimals (including original, reverse and complement)

Signed integers are called fixed-point integers by default , and the default is fixed in the last position.

Fixed-point integer: the decimal point is at the end.

• Encoding includes: original code, inverted code, complementary code, and shifted code.

Fixed-point decimal: the decimal point is one digit after the sign bit.

• Encoding includes: original, reverse, complement.

The original code representation of the fixed-point decimal: determine the bit weight according to the position of the decimal point.

About the complement and complement of fixed-point decimals: exactly the same as fixed-point integers

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1.7.2. Addition and subtraction of fixed-point decimals

Addition and subtraction of fixed-point decimals: exactly the same as fixed-point integers

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1.7.3. Comparison between fixed-point integers and fixed-point decimals (legal range, digit expansion position)

Legal scope :

The position of the digit extension is different : the decimal is directly extended to the end, and the integer is extended to the sign bit

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1.7.4. Addition and subtraction of decimal complement

Addition

Subtraction

Subtraction in fractional complement: consistent with previous integer

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2. Operation method and operation circuit

2.1. Basic computing components

How to use hardware to implement addition is an important question to discuss!

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2.1.1. Know the ALU arithmetic logic unit (including components and ALU instances)

ALU :

ALU control signal components :

• Among them, Ai and Bi represent the input signal, and the corresponding Fi is the output signal.
• The control unit is responsible for analyzing the meaning of instructions. Whether an instruction is an addition, subtraction or other logical operation instruction, the CU will send some control signals after analyzing the instruction, and each signal is a high or low level.

The following is an example of an ALU : 4-bit ALU for the 74181

①M=1 means logic operation (if 0 means arithmetic operation), other s0-s3 means corresponding instruction operation, 4 can represent 16 kinds.

• This chip can support 16 types of logic operations and 16 types of arithmetic operations.

②A and B indicate that 4-bit data can be input, and then the ALU will also output 4-bit output Fi after addition, subtraction, multiplication and division.

③The word length of the machine actually refers to the information (essence) of how many bits can be input at the same time in the ALU.

④ The number of digits of the X register in the corresponding arithmetic unit is usually consistent with the number of digits of the register in the ALU.

⑤The input and output signals of this part are actually designed to be connected in series with other chips, and the specific functions will not be studied for the time being.

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2.1.2. Basic knowledge of circuits

2.1.2.1, logic operation

The most basic logical operation: No matter in complex arithmetic operation or logical operation, it is realized by the most basic logical operation (1 bit)

• Logic operations (essentially high and low levels) implemented by using gate circuits

Through different associative laws we can use different numbers of circuit components to achieve :

• If it appears at the same time as logic and or logic, then it is determined who executes first according to the priority.
• It can be seen that A(C+D) on the left only needs to use two components, while AC+AD on the right needs three components. Then through this example, it can be clearly seen that the simplified logical expression can be Reduce the use of electrical components, thereby achieving cost savings.

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2.1.2.2, compound logic operation

Among them, XOR natural logic can realize addition and parity check.

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2.1.3. Practical application of XOR gate circuit

2.1.3.1. Example of Gate Circuit Realizing Even Parity

Even test : there is an even number of 1s

• XORing an even number of 1s results in 0. Perform XOR on an odd number of 1s and the final XOR result is 1.

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How to achieve it with a circuit ? An example of a gate circuit to find an even parity bit.

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2.1.3.2, XOR gate to realize addition operation (one-bit full adder)

How does the XOR gate implement the addition operation ? A full adder.

通过输入的Ai、Bi以及来自低位的进位Ci-1来去输出得到Si、Ci，这个过程我们是可以使用异或来实现的。

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2.1.3.3、通过一位全加器来实现多位的加法（串行加法器、并行加法器）

第一种：串行加法器

实现过程：输入Ai与Bi接着读取到上次的进位值，进行一位加法器运算，得到的Ci进位值会保存到进位触发器中，之后再次进行一位加法器的时候就可以读取进行运算。

第二种：并行加法器

只有低位的算出来了，高位的才可以去进行计算：

运算速度取决于前一个进位的产生速度。

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知识点回顾与总结

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2.2、深入理解并行加法器的优化（实现并行的突破点）

基于之前的一位加法器，此时要探讨的问题是，如何更快的产生进位？、

原本计算Ci的式子展开可以见下图，每一个Ci都会依赖上一个Ci-1，那么我们是否能够通过一些方式在计算每一个Ci的时候无需使用上一个Ci呢？

• 这就涉及到并行加法器的优化了，我们让Gi = AiBi，Pi = Ai 异或 Bi。

接着重新带入到Ci的式子当中去，举个例子，我们将C₁=G₁+P₁C₀代入到C₂当中去，可以看到C₂的式子：

我们可以惊奇的发现此时C2中仅仅依赖的只是最原始的C₀，按照这样的方法同样带入到其他的C_i当中去呢？同样每一个新的Ci都仅仅只依赖于最原始的C₀，这样子有什么好处？

• 我们这样设想，对于计算Ci我们可以不再依赖之前的串行顺序，而是可以通过并行来进行同时计算多个Ci，直到最后计算完成所有的Ci之后，此时统一再进行处理。

The final composition is the 4-bit CLA adder in the above figure, most of which are composed of FA and some new circuits and operation logic.

So we can summarize the optimization of the parallel adder : Originally, Ci seems to depend on the previous one, which is Ci-1, at the beginning when the formula is not fully displayed. In fact, after we expand, each C _i actually only depends on C ₀ , then the calculation of C _i does not need to follow the serial order, and parallel technology can be used for calculation, until all the calculations of C _i are completed and the calculation process is performed uniformly.

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2.3. Complement code addition and subtraction operator

2.3.1. Principle of adder

The adder mainly includes the lower two input ends of the summand A and the summand B, the right side is the low bit carry, the left side is the highest bit carry, and the top side is the result of the addition:

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2.3.2, Complement code addition and subtraction hardware circuit realization

① Manual calculation method of complement addition and subtraction

Example 1 below: The result of calculating XY is -15, which is actually smaller than the minimum value and overflows

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② Complementary code addition and subtraction hardware implementation (overflow problem needs to be determined by flag bits)

Hardware implementation idea (no flag bit)

The adder below is not only useful for complement addition and subtraction, but also for unsigned addition and subtraction!

The implementation of complement addition and subtraction operations in the machine, the following is also improved in the adder introduced before:

The addition operation is as follows , because it is +, then the Subtraction on the right is 0, and the subtrahend of the Y input is directly transmitted to the adder to participate in the operation because the control signal is 0, at this time, Cin=0 on the right side of the adder, Finally, A, B, and Cin will be added up:

If subtraction is performed , the idea of ​​manual calculation is to invert all the bits of B + 1, how to realize it in the adder at this time?

Because it is a subtraction, the Sub control signal is 1 at this time, then when the Y input comes in, it will take the path of 1, and all bits will be inverted and then passed to the adder. The input value is 1, so it is correspondingly consistent with our hand calculation idea, except that this 1 is passed in by Cin:

The above logical rules are as follows :

But there is still a problem at this time, so how to judge the overflow situation in the process of addition and subtraction ? We give examples for unsigned and signed numbers respectively:

Examples of signed numbers:

Examples of unsigned numbers:

Examples of overflow situations:

无符号数 X=3，Y=4
用4bit表示，X=0011B，Y=0100B
X-Y=0011 + (1011+1) = 1111B=15D ×
解释：实际最终求得的值为-1，而通过目前加法器流程可直接得到15是有问题的

有符号数举例：
4bit补码，X=-8，Y=7
X补 = 1000，Y补=0111
X-Y=1000 + (1000 + 1) = 10001 = 1D
解释：实际最终求得的值为-15，表示数的只有3位，直接溢出了

For the above overflow situation, how does the machine as hardware judge? The following is the flag that we want to introduce.

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③Generation of flag bits (meaning and detailed example explanation)

The four flags are circled as follows:

Four flags :

• OF flag (Overflow Flag overflow flag): It is the XOR result value of the highest bit and the second highest bit. If OF is 1, it means overflow, and if it is 0, it means no overflow. Has nothing to do with the unsigned bit.
• SF flag (Sign Flag): set to 1 when the result is negative, otherwise set to 0. Has nothing to do with the unsigned bit.
• ZF flag (Zero Flag zero flag): the operation result is set to 0, otherwise set to 0.
• CF flag (Carry Flag carry/borrow flag): set to 1 when a carry/borrow occurs, otherwise set to 0 [CF= C out ^ _Sub , where the value of C _out is the highest carry value, Sub refers to addition or subtraction , addition is 0, subtraction is 1], if the final CF is 1, it means overflow. Has no meaning with signed numbers.

Explain one by one according to the above flags :

①Example: For signed numbers, the yellow box below is the highest bit and the second highest bit

No overflow condition:

There is an overflow condition:

②Example: For signed numbers

We can get the SF flag in the purple circle below. If it is 1, it means a negative number, and SF is set to 1. If it is 0, it means a positive number, and SF is set to 0:

③Example: If the n numbers of the final result are all 0, then set it to 1, otherwise set it to 0.

④Example: For unsigned numbers

It is to judge whether overflow is obtained by XORing the value obtained by taking the highest bit carry and whether the current addition or subtraction operation is performed (addition is 0, subtraction is 1). If it is 1, it means overflow, and if it is 0, it means there is no overflow.

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2.4. Shift operations of fixed-point numbers

2.4.1, arithmetic shift

2.4.1.1. Understanding Arithmetic Shift

Multiplication and division operations can be implemented by arithmetic shifting:

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2.4.1.2. Arithmetic right shift and left shift of fixed-point integers and decimals (original code)

Fixed point integer

算数右移（实现除法）：①其中移出2位时，移出去的一位我们可以省去；②移出3位时，由于范围有限，就需要将移出的1省去，此时则丢失精度。

算数左移（实现乘法）：①其中左移2位时，由于2倍乘为160，超过了原本范围的最大数127，此时就会出现计算出错的情况，实际省掉了最前的1。②其中左移3位时再次省略掉了前缀1，此时为-32。

定点小数

定点小数：算数移位与定点整数一致

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2.4.1.3、算数移位（补码）

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2.4.1.4、算数移位的精简总结（原、反、补）

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2.4.1.5、算数移位的应用

通过进行左移操作我们来实现乘法，如下：我们将乘数7可拆分为2的倍乘形式，拆好之后我们实际上可以看做是多个左移运算动作最后进行相加即可求得最终的乘积值

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2.4.2、逻辑移位

2.4.2.1、认识逻辑移位

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2.4.2.2、逻辑移位的应用

对于使用三个bit字节来存储RGB值，可以通过进行逻辑左移来实现移动高8位，中8位，低8位的值，最终相加得到一个完整的RGB。

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2.4.3、循环移位（含介绍与应用）

循环移位：左移与右移移出去的数字会在原本的末尾补上，达到循环的效果

实际应用：通过对一个字形编码其大端到小端之间的状态转换可以使用循环移位。

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知识点总体回顾

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2.5、乘法运算

2.5.1、手算十进制与二进制乘法运算

手算十进制乘法：

手算二进制乘法：

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2.5.2、原码一位乘法

2.5.2.1、硬件机器实现原码一位乘法（详细）

硬件机器实现原码一位乘法：

初始时ACC寄存器会清零：

清零之后MQ的最后一位开始参与运算，最后一位为1，1 * 0.1101，此时进行相加：

00000 + 01101 = 01101

此时开始进行逻辑右移：这一步实际上我们将之前参与MQ最后的一位移除，因为这一位已经用过了所以可直接省略，让ACC的第一位来填充0，方便之后添加新的数据

At this time, the operation we have completed can be shown in the following figure: that is, the product obtained, and then a 0 is added, which is convenient for subsequent arithmetic shift multiplication and addition

At this time, the last bit of MQ is still 1, and then the multiplication operation is performed and the addition operation is performed again. After the addition operation is completed, we perform a logical right shift:

Addition operation:

Logical right shift:

The subsequent process is the same as above, and the product of the remaining numbers is performed...

Finally, the 01011 in the MQ is multiplied and then accumulated into the ACC to complete the final product value:

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2.5.2.2, hand calculation simulation original code multiplication

Hand calculation simulation: In fact, our hand calculation is to simulate the calculation of the machine hardware. The detailed process is shown as follows

1. Obtain the absolute values ​​of x and y, and the initial ACC starts from 0.

2. Use the last bit of MQ to multiply the multiplicand and add ACC, and finally perform a logical right shift operation to complete a round of multiplication.

3. Finally, after the multiplication and accumulation of each number of MQ is completed, we use the multiplier and the symbol value of the multiplicand to perform XOR to determine the flag bit of the multiplication.

The following is an example of decimal multiplication, and it is similar for integer multiplication:

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2.5.3, one's complement multiplication

Comparing with the original code, one-bit multiplication is calculated:

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2.5.3.1, hardware machine realizes one's complement one-bit multiplication

Hardware implementation operation: For MQ, one more bit is added for storing auxiliary bits, and the actual MQ has a total of n+2 bits

In this case, because MQ adds one more bit, one bit will be added to ACC and X at this time, and the extra bit at this time is calculated using double sign bits:

In this process, each addition may be +[x] _complement , +[-x] _complement , this [-x] _complement will have an auxiliary circuit to give us a fast conversion, and then send it to the ALU after being processed by the auxiliary circuit!

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2.5.3.2, Hand calculation analog complement multiplication

The implementation process of hand calculation simulation:

1. The initial ACC starts from 0, the sign bit directly participates in the operation, and one more bit is added to the ACC.

2. By comparing Y _i - Y _i-1 to determine +[x] _complement , 0, +[-x] _complement to add ACC, and finally perform arithmetic right shift to complete a round of multiplication, a total of n+1 wheel.

3. The final obtained value is the final complement multiplication result value.

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Review of Knowledge Points

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The one-bit multiplication and divisor obtained each time is the value closest to the current dividend:

Hand-calculated binary division: each bit is either 0 or 1, and it is constantly pieced together

2.6, division operation

2.6.1, original code division calculation (restoring remainder method and addition and subtraction alternate method)

2.6.1.1, machine hardware simulation to realize the original code division (restoring remainder method and addition and subtraction alternate method)

Machine hardware implementation:

First the chamber of commerce is initialized:

Then, for the recovery remainder method, the computer will directly direct the quotient to 1 by default, and if the obtained ending is negative, it will change the quotient to 0:

After the quotient 1 was found to be negative, the result was changed to 0 and the result is as follows:

At this time, ACC and MQ will perform a unified logical left shift:

The same is true for subsequent steps, and finally the final result can be obtained:

The sign bit is obtained according to the XOR of the sign bits of the dividend and the remainder.

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2.6.1.2, manual division of the original code (restoring remainder method)

Manual calculation simulation restores the remainder method: at the beginning, the direct quotient is 1, if the result is negative, it means that the quotient is wrong and changed to 0, and the subsequent steps are based on the first result value to perform +[y] complement, ₊ [ -y] _{make up} .

You can see that the direct quotient is 1 for the first time. After getting a negative number, we modify it to quotient 0. At this time, we need to recalculate, as follows:

• In fact, the last two left shifts in the above figure are because the direct quotient 1 gets a negative number, so there is no need to restore it. You must pay attention to this point!

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2.6.1.3. Optimizing the Restoration Remainder Method adopts the Alternate Addition and Subtraction Method (also known as the Non-recovery Remainder Method)

**Is there any optimization point for the recovery remainder method? **For example: if the remainder is negative, you can directly quotient 0, and shift the remainder to the left by 1 bit and add |divisor|.

• In this process, the remainder is not restored, but directly skips to the next step. The original code division based on this idea is called the addition and subtraction alternation method (the method of not restoring the remainder).

Extras :

Note : If you use the alternate method of addition and subtraction, you need to add and subtract n+1 times, and shift left n times. If the final remainder is negative, you need the quotient to be 0, and +[|y|] complement to get the correct _remainder .

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Extended description of fixed-point decimal problems (the dividend must be < the divisor)

In the division operation of fixed-point decimals, the final quotient obtained can only be a fixed-point decimal, not an integer. Therefore, in the division operation of fixed-point numbers, we will stipulate that the dividend must be smaller than the divisor. If the dividend is greater than the divisor, the final quotient result must be greater than 1, and the fixed-point decimal cannot be greater than 1. How to check the relationship between the dividend and the divisor for the hardware? ?

• It is mainly determined by the quotient of the first step. If the value obtained by the first +[-|y|] _complement is a positive number, it means that the dividend is > the divisor. At this time, the hardware circuit will stop the operation directly. This kind of division cannot be expressed using fixed-point decimals.
• If it is a negative number, it means that it is normal, and at this time, it means 0 to continue to execute.

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2.6.2 Complementary division calculation (addition and subtraction alternate method)

For the details of complement division, see the right side below, including the details of complement division and about the initial addition and subtraction and the quotient 0/1 situation in the process :

Points to note :

1. The addition and subtraction alternate method of complement code division is somewhat different from the original code. The initial addition and subtraction is based on whether the dividend and the divisor are of the same sign. For the quotient 1 or the quotient 0, it is based on the remainder and the divisor (here the divisor refers to the original title. divisor of the , not the divisor in the procedure).

2. After the last left shift addition is completed, the unified quotient at the end is always set to 1 . The purpose of doing this is to save trouble, and the accuracy error does not exceed 2 ^-n .

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The difference between the original code addition and subtraction alternate method and the addition and subtraction alternate method

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2.7, C language type conversion

For int, short, and long are stored in complement form, using unsigned means it is an unsigned number.

①Short to unsigned short (unsigned to signed number is the same type) : that is, the first bit at the beginning will be regarded as a sign bit, but after converting to unsigned, the first bit will not be regarded as a sign bit

②int to short : that is, 4 bytes to 2 bytes, the high bit is truncated, and the low bit is reserved

③short to int : 2 bytes to 4 bytes

Note: For fixed-point integer complement, if it is a negative number, then all high bits are filled with 1, and if it is an integer, all high bits are filled with 0.

④unsigned short to unsigned int : 2 bytes to 4 bytes

Note: There can be a comparison with ③ here. If it is a positive number and its sign bit is 0, then the high bit is also filled with 0.

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2.8. Data storage and arrangement

2.8.1, big and small endian mode

For the big and small endian mode, the order of storing several word contents is actually different:

• Big-endian mode: 4 bytes are stored in memory addresses in the specified sequence from front to back.
• Little-endian mode: 4 bytes are stored in the memory addresses in the specified sequence from the back to the front.

Why is little-endian storage more suitable for machine processing?

• For example, when performing an addition operation, the operation is usually performed from the low bit, while the storage method of the little endian mode is stored from the low bit to the high bit, and the reading is performed in the order of increasing memory, so it is in line with computer storage. Way.

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2.8.2. Understanding computer addressing

Assuming that the storage word length is 32 bits, a word is 32 bits, and a half word is 16 bits. Each memory access can read/write a word, which is a large part of the 32 bits circled below. The computer uses one byte to address:

If addressing is based on bytes, let me tell you to address according to the specified word, we can convert the word into a byte and then determine the specific location: for example, the length of the stored word is 32 bits, and the word is 32 bits at this time, and the byte It is 8 bits, let you find the word number 2, we first convert 2 to binary bit 10, and then logically shift left by 2 bits to get 1000, which is equivalent to *4 at this time, so as to determine the exact address position.

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2.8.3. Boundary alignment and boundary misalignment Boundary alignment

现在有一个场景：我们依次写入3个字节，接着写入3个半字，对于这种情况采用边界对齐与不对齐方式就会影响我们的实际存储方式。

边界对齐如下表所示：

• 由于一个字长为32位，此时一行相当于可以存储4个字节，按照上述场景，我们依次写入3个字节后，要写入一个半字，此时由于剩余的一行只剩余一个字节了，由于我们采用的是边界对齐方式，会将这一个半字写入到下一行当中。

边界不对齐如下表所示：

• 由于一个字长为32位，此时一行相当于可以存储4个字节，按照上述场景，我们依次写入3个字节后，要写入一个半字，此时由于剩余的一行只剩余一个字节了，由于我们采用的是边界不对齐方式，会继续存储到这一行中直至塞满这一行，此时这一行最后8位存储的是半个字。

为什么有两种方式存储呢？区别

• 采用边界对齐方式：空间换时间，若是读取上述的第一个字时，只需要访存一次即可，直接读取第二行。
• 采用边界不对齐方式：可以有效的利用存储空间，不浪费，但是对于我们要读取指定的一个字时，由于一个字拆分两部分一部分存储第一行最后，另一部分存储在第二行中，那么由于我们读/写是一个字一个字，此时就需要两次访存，时间开销就变大了。

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三、浮点数的表示与运算

浮点数的局限性如下：

认识十进制的科学计数法：

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3.1、浮点数的表示

3.1.1、认识浮点数的表示

二进制的浮点数原理：

针对于阶码与尾数对应表示的含义：

实际案例：根据给出的阶码尾数来表示求a，b的真值。

例1：

If 1B is used to store the true value of a at the end, it can be expressed just right, the order code is 001, the mantissa is 11001, and the combination is exactly 8 bits.

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3.1.2. Normalization and examples of floating point numbers

Example 2: Lead to the normalization of the mantissa of a floating-point number

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Introduce the normalization of decimal scientific notation :

• There are two ways to represent a decimal digit, and the final representation should be +3.026, although the other 0.003 can also be represented, but it loses precision.
• Scientific notation stipulates that the highest bit is an effective value and cannot be 0. When the mantissa is the same length, it is stipulated that the highest bit of the mantissa cannot be 0 as much as possible.

Then go back to Example 2: We can shift the mantissa to the left by one bit, and at this time, one bit should be subtracted from the exponent. The purpose of this is to preserve as much precision as possible

Normalization of the mantissa of floating-point numbers : understanding left and right rules

• It is necessary to determine when to use the left gauge and the right gauge. When denormalizing, arithmetic left shift is required, and arithmetic right shift is performed if overflow occurs.

Planning example :

The sign bit of the mantissa is 01. At this time, the overflow situation can be saved by using the right rule.

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3.1.3. Characteristics of normalized floating-point numbers

The characteristics of normalized floating-point numbers : original code, complement code

Note: Negative numbers with complementary codes indicate that the mantissa should be normalized in the form of 1.01xxxx.

Example: 1.1110100 shown in the figure below is not a normalization requirement, because it is a negative complement and should be in the form of 1.01xxxx, so arithmetic left shift is required at this time.

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3.1.4, the range of floating point numbers

As shown in the figure below: if it is smaller than 0.00001, then it can be expressed as positive underflow at this time; and for negative underflow, it can be expressed if the absolute value has exceeded the minimum range.

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Review of Knowledge Points

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3.2, IEEE 754 (floating point standard)

3.2.1. Representation and definition of frame shift in IEEE 754

The IEEE 754 intermediate code is expressed by shifting code:

• Note that frame shifting can only be used to represent integers, which is one of the reasons why the order code is represented by frame shifting.

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3.2.2. Definition of frame shift (for example, when the offset value is 128 and 127)

The most original definition of frame shifting : frame shifting = true value + offset (the true value here refers to the original code value)

The mantissas in the following examples are expressed in two’s complement notation :

①The case where the offset value is 128D

Here we give a set of truth value, complement code and frame shift. The frame shift in the table can be obtained by our above formula:

②The case where the offset value is 127D

When the offset value is 127D, the far right in the table on the left is the frame shift corresponding to the true value. Let’s first try to calculate the first -128 frame shift. You can see that it is a subtraction calculation, the subtrahend<subtrahend , at this point we can add one more bit

• In this case, the frame-shift value is as shown in the courseware above except that the first number is 255, and the following ones are 1-254.

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3.2.3, IEEE 754 standard floating-point representation

Here, the exponent code adopts code shifting, and the mantissa is represented by complement code .

• For the value of the mantissa in float is 23 bits, it actually refers to M in 1.M, and this 1 is there by default.

Take float as an example :

①The true value range of its order code is -126-127, which is determined according to the offset value. The missing two are -128 for all ones, and -127 for all 0s. These two states will be used as special processing.

• You can look at the first and second rows of the last column in the previous figure, all 1 or all 0.

• How to calculate the offset value of float decimal? 2 ⁸ - 1 - 1 = 127.

Let's look at a case of normalizing a floating-point number to find the truth value:

②double type:

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3.2.4. Actual case calculation (example of mutual conversion between true value and single-precision floating-point number)

1. Given the true value, let you find the representation of the single-precision floating-point number format

• Since IEEE 754 implies 1. for the integer part of the mantissa, it must be converted to 1.xxxx here.

2. Given a single-precision floating-point number format, let you find the true value

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3.2.5, IEEE 754 single-precision floating-point type with different order codes and mantissas (maximum value, minimum value)

What is the minimum absolute value and maximum absolute value that IEEE 754 single-precision floating-point type can represent?

The following are the values ​​obtained in different cases of various exponent codes and mantissas:

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Knowledge point review summary

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3.3 Calculation of floating point numbers

3.3.1. Addition and subtraction of floating point numbers

Take the decimal system as an example and the steps are as follows :

① Matching steps: the small steps are aligned with the large steps.

• If it is not aligned with the large order, then the value of the mantissa will be very large, and each large bit will occupy one more position, for example, the original 0.9854 x 10 5 , if the order becomes ^smaller , it will be 985.4 x 10 ² , at this point you can see that there are three more digits in the mantissa, but what if it is only in the order?
  • Here is the original code: originally 5 is 101, and now it is 2 and it is only 10. At this time, one less digit is exchanged for three more digits, which is definitely not good. This is also one of the reasons why the above-mentioned does not align with the large steps.
  • It is also convenient for the computer to process the mantissa.

②Mantissa addition and subtraction

③Normalization: Ensure that the first numerical digit of the mantissa has a valid digit.

④ Rounding: The bits of the mantissa are limited, and the addition, subtraction and truncation of the mantissa may be too long, so rounding is required. There are various strategies for rounding.

⑤ Judgment of overflow: If the step code exceeds the specified range, it will overflow.

Note: If overflow is judged in step ⑤, we can save it in step ③④.

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3.3.2. Practical cases of addition and subtraction of floating point numbers

Actual cases of addition and subtraction of floating point numbers:

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3.3.3, rounding situation

Two input methods :

① 0 rounding method

The example is as follows: For the following example, it is +1 at the end, which is 01 originally, and 10 after +1

②Constant setting 1 method

Note the following points :

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3.3.4. Mandatory type conversion problem

Most of the exams are 32-bit, and the current mainstream is 64-bit.

Lossless conversion, data precision will not be lost

There will be a loss of precision when converting int to float : where int is 1+31, and float is 1+8+23, where 23 actually implies one bit (it can represent 1+23=24 bits)

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Review of this section

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Organizer: Long Road Time: 2023.5.22-5.2