Principles of computer composition - storage system (super detailed, must see!!)

• This article is a study note of the principles of computer composition in 2021 for Wangdao's postgraduate entrance examination . I hope it will be helpful to everyone.

3. Storage system

3.1 Basic concepts

Knowledge overview:

1. Memory hierarchy

Main memory-auxiliary storage: solves the problem of insufficient main memory capacity.

Cache - main memory: solves the problem of speed mismatch between main memory and CPU.

2. Classification of memory

(1) Classify by level

(2) Classification by transmission medium

• Semiconductor: main memory, Cache
• Magnetic Surface Storage: Disk, Tape
• optical storage

(3) Classify by access method

• Associative memory: It can be retrieved to the storage location for reading and writing according to the content.
• Random Access Memory (RAM): The time required to read and write to any one memory location is the same regardless of location. (Memory)
• Sequential Access Memory (SAM): The time required to read and write a memory cell depends on where the memory cell is located. (tape)
• Direct Access Memory (DAM): It has both random access and sequential access characteristics. First directly select the area where the information is located, and then access it sequentially. (mechanical hard disk)

Both sequential access memory and direct access memory are classified as serial access memory (reading time is related to data location).

(4) Classify according to the changeability of information

• Read and write memory: readable and writable (such as memory, hard disk, etc.)
• Read-only memory: can only be read, not written (such as discs used in movies)

(5) Classify according to the storability of information

• Volatile memory: data disappears after power failure (main memory, Cache)
• Non-volatile memory: save when power off (disk, CD)
• Destructive readout: after reading out data, it needs to be rewritten (such as DRAM chip)
• Non-destructive readout: the original data is not destroyed after the data is read out (such as SRAM chips, magnetic disks, optical disks)

3. Memory performance indicators

• Storage capacity: number of storage words x storage word length (such as 1M x 8 bits).

MAR reflects the number of stored words, and MDR reflects the stored word length.

• Unit cost: price per person = total cost/total capacity (the price of a memory stick is 259, and the capacity is 8GB, then unit cost = 259 / (8*8) ).

• Storage speed: data transfer rate = data width/storage cycle

  

• Access time: access time + recovery time = access cycle, the computer needs a period of recovery time after a read and write operation before the next read and write operation can be performed.

• Main memory bandwidth: It is the above data transfer rate, which means the maximum amount of information entering and leaving the main memory per second, and the unit is word/second, byte/second, bit/second.

3.2 Main memory

3.2.1 Basic composition of main memory

Knowledge overview:

(1) storage body

A memory bank is composed of a plurality of storage units, and each storage unit is composed of a plurality of storage elements.

Storage element: Capable of storing a single bit.

Capacitor: store charge, a voltage difference indicates a bit 1, and no voltage difference indicates a bit 0.

MOS tube: An electronically controlled switch. When the input voltage reaches a certain threshold, the MOS tube can be turned on, and the charge in the capacitor can be released. (equivalent to a switch of a circuit)

A storage unit is formed by combining multiple storage units, and the storage units of the same storage unit share one MOS tube.

A memory bank is formed by combining multiple memory cells.

(2) Address register and data register

Which storage unit is selected for reading and writing by a decoder .

And transmit data through the data bus.

(3) Control circuit:

The control circuit controls the data processing of MAR, decoder and MDR.

At the same time, the memory chip also needs to provide chip select lines, read select lines, and write select lines.

Chip selection line: the main switch of the chip, when the low level is active, it means that the chip is selected for work.

Read selection line, write selection line: respectively used to control whether to read or write. Sometimes these two lines are combined into one, with a low level for writing and a high level for reading.

(4) On the whole:

Here also shows the role of the chip selection line. The above-mentioned memory bar is composed of multiple memory chips. Assuming that each memory chip is 1GB, the memory bar is 8GB. When reading and writing data, it is necessary to use the chip selection line to select different memory chips for storage .

Addressing:

Assuming that the storage word length in the storage bank is 4B and the total capacity is 1KB, there are 256 storage units.

There are four addressing modes:

• Addressing by byte: there are 1K addresses, and 10 address lines are required
• Addressing by word: There are 256 addresses, and the byte address is equal to the word address multiplied by the word length.
• halfword addressing
• addressing by double word

3.2.2 Random Access Memory RAM

Knowledge overview:

There are two main types of RAM:

SRAM : Static RAM, used for Cache

DRAM : Dynamic RAM, used for main memory

1. Differences in characteristics caused by different storage elements

DRAM chips: use gate capacitance to store information

SRAM chips: use flip-flops to store information

(1) Gate capacitance:

1: Charge is stored in the capacitor

0: No charge is stored in the capacitor

Destructive readout : After the capacitor is discharged, it is equivalent to the charge running out, resulting in information destruction, so a rewrite operation is required after reading out, also known as regeneration. This is why the read and write speed of DRAM is slower than that of SRAM.

The charge in the capacitor can only last for 2ms , even if the power is not turned on, the information will disappear after 2ms. Therefore, it must be refreshed once within 2ms to charge the capacitor.

The manufacturing cost of each storage element is lower, the integration degree is high, and the power consumption is low.

(2) Bistable flip-flop:

1: A is high and B is low

0: A is low and B is high

Non-destructive readout : After the data is read out, the state of the flip-flop remains stable without rewriting. Read and write faster.

As long as the power is not turned on, the state of the flip-flop will not change.

The manufacturing cost of each storage element is higher, the integration level is low, and the power consumption is high.

2. Refresh of DRAM

(1) How often to refresh: generally 2ms

(2) How many memory cells are refreshed each time: In row units, one row of memory cells is refreshed each time.

The arrangement of the storage cells in the memory is jointly selected by the row address decoder and the column address decoder .

If only one decoder is used for address selection, then 8-bit addresses need to use 2 ⁸ =256 gate lines, and if the row address decoder and column address decoder work together, only 2 4 +2 ⁴ = ³² gate lines are needed, that is, 16 gate lines for the row decoder and 16 gate lines for the column decoder.

(3) How to refresh: With hardware support, read out a line of information and rewrite it, which takes up one read/write cycle .

(4) When to refresh?

Assuming that the internal structure of DRAM is arranged in the form of 128x128, and the read/write cycle is 0.5us, there are 2ms/0.5us=4000 read/write cycles in 2ms.

Therefore, there are three ways to choose the refresh time:

3. DRAM address line multiplexing technology

Due to the large storage capacity of DRAM and the large number of storage units, more address lines are required. In order to simplify the hardware, the address line multiplexing technology is adopted, and the row address and column address are divided into two and sent to the decoder.

Summarize:

3.2.3 Read Only Memory ROM

• Although the ROM chip is called "Read Only", many ROMs can also be written.
• Flash writes are generally slower than reads because they need to be erased before writing.
• In fact, many ROMs also have the characteristics of random access.

3.2.4 Connection between main memory and CPU

1. The connection between a single memory chip and the CPU

Assume that there is an 8Kx1-bit memory chip, which means that the chip needs 13 address lines, and the CPU has 8 data lines and 16 address lines. It can be seen from the above that the CPU can only transmit 1 bit of data to the chip at a time, which will cause the data lines of the CPU to not be fully utilized, and there may be cases where the main memory capacity needs to be expanded.

Therefore, it is necessary to expand the main memory capacity by rationally connecting multiple memory chips.

There are two ways:

• Bit extension: Extend the word length of the memory unit
• Word extension: expand the number of storage units

2. Connection between multiple memory chips and CPU

(1) Bit extension:

As shown in the figure above, when two memory chips are connected, the CPU address bus A0~A12 will be sent to the two chips together, and the data line D0 of the second chip will be connected to the data line D1 of the CPU. In this way, it is expanded into a memory of 8Kx2 bits.

Similarly, there are a total of D0~D7 data lines in the CPU, so a total of 8 memory chips shown in the figure can be connected to expand into 8Kx8-bit memory.

(2) Word expansion:

There are two types of word extensions:

• line selection
• chip selection

As shown in the figure, it is an 8Kx8-bit memory chip. Since the word length of the memory unit of the chip is equal to the number of data buses of the CPU, no bit expansion is required. The address lines are not fully utilized, so word expansion can be considered.

1. Line selection method:

Use a special address line as a chip select line to select a certain memory chip.

As shown in the figure: A13 is the chip select line of the first memory chip, and A14 is the chip select line of the second memory chip. When A13 and A14 are respectively 01 or 10, it means that the first memory chip or the second memory chip is selected, so that the number of memory units can be expanded.

At this time, the lowest address of the first memory chip is: 01 0000 0000 0000, and the highest address is 01 1111 1111 1111

The lowest address of the second memory chip is: 100 0000 0000 0000, and the highest address is 101 1111 1111 1111

But there is a defect in the line selection method: A13 and A14 cannot take 00 or 11 , because taking 00 will cause neither of the two fast memory chips to be selected, and 11 will cause both of the two memory chips to be selected. And n chip select signals are needed.

Can be optimized:

Selection is done only through A13 and a NOT gate.

At this time, the lowest address of the first chip is 10 0000 0000 0000, and the highest address is 11 1111 1111 1111

The lowest address of the second chip is 00 0000 0000 0000 and the highest address is 01 1111 1111 1111

2. Chip selection method:

Summarize:

(3) Simultaneous expansion of bit expansion and word expansion

3.2.5 Dual-port RAM and multi-block memory

Knowledge overview:

• Access cycle = access time + recovery time

As mentioned above, due to the characteristics of capacitance, DRAM needs to be rewritten after each read operation, that is, it needs a certain recovery time, resulting in a relatively long DRAM access cycle, and this recovery time is often longer than the access time.

This leads to two problems:

1. For today's computers, many of them have multi-core CPUs, so when different CPUs access the main memory, does the subsequent CPU need to wait for such a long recovery time?

2. The reading and writing speed of the CPU is much faster than that of the main memory. What should I do if the recovery time of the main memory is too long?

These two questions correspond to what follows: dual-port RAM and multi-block memory, respectively.

1. Dual port RAM

**Two sets of completely independent data lines, address lines, and control lines are required. **There are also more complex control circuits in the CPU and RAM.

Two ports operate on the same main memory in the following four situations:

When a conflict occurs, a busy signal will be sent, and a judgment logic decides to temporarily close a port (that is, be delayed), and the unclosed port is accessed normally, and the closed port is extended for a short period of time before accessing.

2. Multi-module memory

(1) Multi-body parallel memory:

Each square in the figure represents a storage unit.

High-order cross addressing: After each memory bank has been traversed, the next memory bank is traversed. It is only equivalent to expansion.

Low-order interleaved addressing: Traversing memory banks in a horizontal manner, that is, traversing different memory cells of different memory banks each time. In this way, when reading the storage units of other storage banks, the previously read storage units can use this time to recover, achieving a parallel effect.

In the selection of the number of modules, it is necessary to ensure that the number of modules m >= T/r , so as to ensure that the memory bank has enough time for recovery.

(2) Single multi-word memory:

Contrary to the multi-body parallel memory, the single multi-word memory combines multiple memory banks, and can only fetch m words at the same time at a time, and cannot fetch one of them alone. When the data read and written in a certain time are in different rows, redundant information needs to be read in.

3. Application

Dual channel memory:

Principle: Low-order cross-addressed multi-bank parallel memory.

3.3 Cache

3.3.1 Basic concepts and principles of Cache

Knowledge overview:

Although dual-port RAM and multi-module memory have improved the working speed of the memory, there is still a large gap with the CPU, so the cache Cache is produced, which has a higher price and a lower capacity.

(1) Working principle:

**Spatial locality: **Information to be used in the near future is very likely to be close to the information being used by idlers in terms of storage space. (The storage of information is generally sequential)

**Temporal locality:** Information that will be used in the nearest future is likely to be used now. (There are likely to be a large number of loop structures in the program, which need to be accessed repeatedly)

Therefore, the theoretical basis for the Cache to work: From the above two localities, we can analyze that we can put some data around the address currently accessed by the CPU into the Cache.

(2) Performance analysis:

Let **t _c ** be the time required to access the Cache once, and **t _m ** be the time required to access the main memory once.

The CPU can directly find the required information in the Cache, which is called a hit.

**Hit rate H: **The ratio of the information that the CPU wants to access is already in the Cache.

** Missing Rate (Miss Rate) M: ** M = 1 - H

**CPU average access time t is: **t = H t _c + ( 1-H ) ( t _c +t _m )

example:

(3) How to define "around":

• The storage space of the main memory is divided into blocks , and data exchange is performed between the main memory and the Cache in units of blocks .

• In this way, the main memory address can be divided into two parts: the block number and the address within the block.

• In the operating system, "a block" in main memory is usually also called "a page/page/page frame".

• A "block" in the cache is also called a "row".

There are still some problems between Cache and main memory:

• How to distinguish the data block correspondence between Cache and main memory? ——The mapping method of Cache and main memory
• Cache is small and main memory is large. What if the Cache is full? ——replacement algorithm
• The CPU modifies the data copy in the Cache, how to ensure the consistency of the data master copy in the main memory? ——Cache write strategy

Please continue to read the above questions.

Summarize:

3.3.2 Mapping method of Cache and main memory

(1) Fully associative mapping

Any main memory block can be placed anywhere in the Cache.

Add a mark bit to each Cache block to record the corresponding main memory block number.

A valid bit is also needed . When the valid bit is 1, it means that the marking bit is valid, and when the valid bit is 0, it means that the marking bit is invalid.

The above figure is an example, any piece of data in the main memory can be stored in any piece of Cache, as long as the corresponding data with the main memory is marked. For example, the data of block No. 9 in the main memory can be stored in any position from No. 0 to No. 1 in the Cache.

Advantages: Cache storage space is fully utilized and the hit rate is high.

Disadvantage: The search speed is slow.

Therefore, the process of CPU accessing main memory data is as follows:

(2) direct mapping

Each main memory block can only be placed in a specific location: Cache block number = main memory block number% total number of Cache blocks.

Take the above picture as an example, 8 blocks are a cycle. The data of blocks 0 and 8 in the main memory can be stored in block 0 of the cache, the data of blocks 1 and 9 in the main memory can be stored in block 1 of the cache, and so on.

**If the total number of Cache blocks = 2 ⁿ , then the last n bits of the main memory block number directly reflect its position in the Cache. **This is because Cache block number = main memory block number% Cache total block number = last n digits of main memory block number.

Therefore, for the tag numbers stored in the Cache, it is not necessary to save the corresponding entire address in the main memory, and only the (mn) binary numbers in front of the main memory block number m can be reserved.

Therefore, the process of CPU accessing main memory data is as follows:

Advantages: Only one mark needs to be compared, and the speed is the fastest.

Disadvantages: Cache storage space is insufficient, and the hit rate is low.

(3) Group associative mapping

Cache blocks are divided into several groups, and each main memory block can be placed in any position in a specific group.

Group number corresponding to each main memory block = main memory block number% number of groups

Take the above picture as an example, 8 blocks are a cycle group. No. 0 and No. 8 belong to Group 0, and the data of No. 0 and No. 8 can be stored in any position of Group 0, as long as they are marked.

Like direct mapping, if the total number of groups in the Cache = 2 ⁿ , the n bits at the end of the main memory block number directly reflect which group it is in the Cache.

Therefore, the process of CPU accessing main memory data is as follows:

Assume that the following 2-way group associative mapping is used, that is, 2 blocks are divided into four groups.

Advantages: A compromise between the above two methods, the overall effect is better.

Summarize:

3.3.3 Cache replacement algorithm

Knowledge overview:

In the direct mapping method, since the Cache block corresponding to the main memory data block is fixed, there is no choice, and no replacement algorithm is needed.

The fully associative mapping and group associative mapping methods need to use a replacement algorithm for replacement because different positions can be selected for replacement.

The following example uses fully associative mapping as an example.

1. Random algorithm (RAND)

• If the Cache is full, a block is randomly selected for replacement.

  Example:

  Red in the figure indicates that the position has been replaced with a new block.

  Green in the figure indicates that the cache block is hit.

• The implementation of the random algorithm is simple, but the locality principle (time locality) is not considered at all, the hit rate is low, and the actual effect is very unstable.

2. First in first out algorithm (FIFO)

• If the Cache is full, replace the block that was loaded into the Cache first.

Example:

As can be seen from the figure above, the red color appears many times, which indicates that the cache block is frequently replaced, and the block that has just been replaced is quickly reloaded, which is called jitter phenomenon.

• The first-in-first-out algorithm is simple to implement, but still does not consider the principle of locality (time locality), because the block that is first transferred into the Cache may also be frequently accessed.

3. Least Recently Used (LRU)

• Set a "counter" for each Cache block to record how long each Cache block has not been accessed. When the Cache is full, replace the "counter" with the largest one.
• Counting rules:
  • When hit, the counter of the hit line is cleared, the timer lower than it is added by 1, and the rest remain unchanged (adding one is meaningless).
  • When there is a miss and there are idle rows, the counter of the newly loaded row is set to 0, and the rest of the non-idle rows are all incremented by 1.
  • When there is a miss and there is no free row, the information block of the row with the largest count value is eliminated, the counter of the block of the newly installed row is set to 0, and the rest are all added to 1.

Example:

At the beginning, there is no data stored in the cache block, and the counters are all 0.

Access main memory block 1

Access main memory block 2

Access main memory block 3

Access main memory block 4

Access main memory block 1, hit cache, Cache0 counter is reset to zero

Access main memory block 2, hit, Cache1 counter is reset to zero

When accessing main memory block 5, if there is a miss at this time, the first-in-first-out algorithm will be adopted to replace the block with the largest count value, and Cache2 will be replaced in the figure

The following process is similar to the above, and only needs to be simulated according to the counting rules, so I won’t go into details here.

• The least recently used algorithm is based on the principle of locality. Main memory blocks that have been accessed recently are likely to be accessed in the next period. Therefore, it is reasonable to eliminate blocks that have not been accessed for the longest time. The algorithm actually works well and has a high Cache hit rate.
• If the number of frequently accessed main memory blocks > the number of Cache lines, thrashing may still occur.

4. Infrequently Recently Used (LFU)

• Set a "counter" for each Cache block to record how many times each Cache block has been accessed. When the Cache is full, replace the one with the smallest "count value".

• The newly transferred block counter = 0, and the counter is +1 every time it is accessed.

Example:

After accessing the main memory blocks No. 1, No. 2, No. 3, and No. 4, the status of the Cache:

When accessing blocks 1 and 2 of the main memory, they both hit, and the counters of Cache0 and Cache1 are incremented by one. When accessing the main memory block No. 5, there is a miss, so the Cache2 with the smallest count value will be replaced (here, both Cache2 and Cache3 are 0, and it will be selected according to the row number increment or FIFO strategy)

The following process is similar to the above, and it can be simulated by itself according to the least frequently used algorithm, so I won’t repeat it here.

• Evaluation: The memory blocks that have been frequently accessed may not necessarily still be accessed in the future, and the locality principle (time locality principle) is not well followed, so the actual effect is not as good as the least recently used algorithm LRU.

Summarize:

3.3.4 Cache write strategy

Knowledge overview:

Why not discuss the read hits and read misses?

Because reading will not cause data inconsistency between main memory and Cache.

1. Write hit

(1) Write back method:

• When the CPU writes a hit to the Cache, it only modifies the content of the Cache and does not write it into the main memory immediately, and writes it back to the main memory only when the Cache block is replaced.

• A dirty bit needs to be added to mark whether the Cache block has been modified.

• The number of memory accesses is reduced, but there is a hidden danger of data inconsistency.

(2) Full writing method:

• When the CPU writes a hit to a Cache block, the data must be written into the Cache and the main memory at the same time, and a write buffer is generally used.
• The number of memory accesses increases and the speed becomes slower, but the consistency of data can be guaranteed.

• Using the write buffer, the CPU writes very fast. If the write operation is infrequent, the effect is very good. If the write operation is frequent, it may be blocked due to the write buffer saturation.

2. Write miss

(1) Write allocation method:

• When the CPU misses writing to the Cache, it transfers the block in the main memory into the Cache and modifies it in the Cache, which is usually used with the write-back method. That is, it is written back to main memory only when a replacement occurs.

(2) Non-write allocation method:

• When the CPU misses writing to the Cache, it is only written to the main memory and not transferred to the Cache. Use with full lettering.

3. Multi-level Cache

Modern computers often use multi-level Cache:

• The closer to the CPU, the faster the speed and the smaller the capacity

• The farther away from the CPU the slower the speed and the greater the capacity.

The all-write method + non-write allocation method is often used between all levels of Cache.

The write-back method + write-allocation method is often used between Cache and main memory.

Summarize:

3.4 Virtual storage system

3.4.1 Page storage

Sometimes a program is too large to store it sequentially in each block of main memory, so the operating system will divide it into several pages, the size of the page is the same as the size of the block, and each page can be discretely placed in a different block of main memory.

Logical address (virtual address): The address seen by the programmer.

Physical address (real address): The actual address in main memory.

For a machine instruction: 000001 001000000011 (operation code + address code), the address code uses the logical address.

Page table: It records which main memory block each logical page is stored in, and the data of the page table is stored in the main memory.

Address translation process: an example

Assume that an instruction fetch operation is performed at this time, the instruction is 000001 001000000011 , so the logical address of the data to be fetched is 001000000011

1. First, the logical address is split into logical page number and in-page address .
2. Find the page table in the main memory , and then look up the table through the logical page number to find out the corresponding main memory block number .
3. The main memory block number is spliced ​​with the address in the page to obtain the final physical address .
4. Find the physical address in the Cache, and if you can't find it, go to the main memory to find it.

However, since the page table is stored in the main memory, according to the principle of time locality, the data just used is likely to be used later, so the next time the data is used, the main memory must be accessed again for table lookup. In order to look up the table faster, the recently accessed page table entries will be placed in a higher-speed memory, called a fast table .

**Quick table: **Quick table is a kind of associative memory, which can be searched according to the content, and it uses SRAM, so the access speed is faster.

The difference between fast table and Cache:

• Fast tables store copies of page table entries
• The cache stores a copy of the main memory block

Summarize:

3.4.2 Virtual memory

**Virtual storage system: **The data in the auxiliary storage is not loaded into the main memory all at once, but similar to the Cache-main memory, a part of the data is loaded into the main memory according to the principle of locality.

For example: behind the "Loading" interface when playing a game, it may be that the data related to the game map is loaded into the memory.

1. Paged virtual memory

Similar to Cache and main memory, data in auxiliary memory is also divided into blocks one by one.

In order to load only part of the data into the main memory, some information needs to be added to the page table.

• Logical Page Number: The page number in the logical address

• Main memory block number: The main memory block number in the physical address

• External storage block number: the corresponding block number in the auxiliary storage

• Valid bit: whether this page is loaded into main memory

• Access bit: used for the page replacement algorithm. When the main memory is used up, it needs to be replaced. For example, the least frequently used algorithm can be used to count the number of accesses.

• Dirty bit: Whether this page has been modified. After modifying the main memory, data inconsistency between the main memory and the auxiliary memory will result.

Since the transfer of data between the main memory and auxiliary memory is regulated by the operating system , please refer to the relevant content of the operating system for details, and the above is only a rough introduction.

• **Main memory-auxiliary storage: **A virtual storage system is realized, which solves the problem of insufficient main memory capacity.
• **Cache——main memory:** Solve the problem of speed mismatch between main memory and CPU.

2. Segmented virtual memory

Split according to functional modules.

For example: #0 section is your own code, #1 section is the code of the library function, #2 section is the variable.

Similar to paging storage, the operating system determines which segments should be transferred into memory in units of segments .

3. Segment page virtual memory

The program is divided into sections according to functional modules, each section is then divided into pages of fixed size, and the main memory space is also divided into pages of equal size.

The call-in and call-out of the program to the main memory still takes the page as the basic transfer unit, each program corresponds to a segment table, and each segment corresponds to a page table.

Virtual address: segment number + page number in the segment + address in the page.

For details, please refer to the operating system content.