Android Ethernet debugging is mainly divided into gmac and pcie interfaces. The main representatives are RealTek's 8211 series and 8111 series. This article mainly analyzes the 8211 connected to Gmac.
For example, 8211F is the Phy connected to GMAC, which is reflected in the schematic diagram, and 19-22 IOs are all connected to the GMAC of the main control IC
Note in the picture above that GMAC is connected to GMAC1. Generally, rockchip 3568 has 2 sets of GMAC interfaces, namely GMAC0 and GMAC1.
Example: use GMAC1
The unused GMAC0 and the unused GMAC0 IO are used for other functions, here is the multiplexing function of io.
As long as you notice the Ethernet chip, that is, the interface connecting the PHY and the main control is the one.
The schematic diagram shown below is for attention 1 power control 2 reset control 3 other controls
1 The power supply part needs to pull up LAN_WAKE_EN_N so that 8211 can supply power, this step is very important.
2 About reset Many ICs need to perform a reset action before they can work normally when they are turned on, and this step is also very important.
The schematic shown here is high effective, and the default is low
DTS configuration:
The reason why the above schematic diagram is described is to configure in DTS. The port mentioned in the above description is GMAC1, power controls IO, and reset controls IO
In DTS, snps, reset-gpio fill in the corresponding pins for the reset IO. The power of the IC will be realized by itself according to the difference in the schematic diagram. The default schematic diagram does not have this control. If you write a driver yourself, it will pull up the IO when it is turned on.
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
snps,reset-active-high;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
&gmac1m1_clkinout>;
//8211
tx_delay = <0x63>;
rx_delay = <0x31>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};&gmac {
phy-supply = <&vcc_phy>; ---PHY 供电由&vcc_phy 提供，见后续说明
phy-mode = "rgmii"; --- rgmii 或 rmii， pinctrl-0 字段必须与此字段相匹配
clock_in_out = "input"; --- input: 时钟由 PHY 输入给 MAC，output: 与 input 相反
snps,reset-gpio = <&gpio2 15 GPIO_ACTIVE_LOW>; ---用于复位 PHY 的 GPIO
snps,reset-active-low; ---复位 PHY 的GPIO 低有效
snps,reset-delays-us = <0 10000 50000>; ---表示复位PHY 前的延时为 0ms，拉低维持的时间为 10ms, 拉高后延时 50ms
assigned-clocks = <&cru SCLK_MAC>; ---MAC 的时钟源
assigned-clock-parents = <&ext_gmac>; ---MAC 父时钟由&ext_gmac 提供，见后续说明
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>; ---设为&rgmii_pins 或&rmii_pins， 必须和 phy-mode 字段匹配
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "okay";
};Here we will focus on some IO multiplexing configurations of gmac1m1_miim under pinctrl-0. Generally, we first look at the schematic diagram, which is the one connected to the main control, as shown in the GMAC1 above.
GPIO3_D6 ~ GPIO4_B1 are part of GMAC1, open under kernel\arch\arm64\boot\dts\rockchip
rk3568-pinctrl.dtsi View 3 RK_PD6 found here in gmac1:
gmac1 {
/omit-if-no-ref/
gmac1m0_miim: gmac1m0-miim {
rockchip,pins =
/* gmac1_mdcm0 */
<3 RK_PC4 3 &pcfg_pull_none>,
/* gmac1_mdiom0 */
<3 RK_PC5 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m0_clkinout: gmac1m0-clkinout {
rockchip,pins =
/* gmac1_mclkinoutm0 */
<3 RK_PC0 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m0_rx_er: gmac1m0-rx-er {
rockchip,pins =
/* gmac1_rxerm0 */
<3 RK_PB4 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
rockchip,pins =
/* gmac1_rxd0m0 */
<3 RK_PB1 3 &pcfg_pull_none>,
/* gmac1_rxd1m0 */
<3 RK_PB2 3 &pcfg_pull_none>,
/* gmac1_rxdvcrsm0 */
<3 RK_PB3 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
rockchip,pins =
/* gmac1_txd0m0 */
<3 RK_PB5 3 &pcfg_pull_none_drv_level_2>,
/* gmac1_txd1m0 */
<3 RK_PB6 3 &pcfg_pull_none_drv_level_2>,
/* gmac1_txenm0 */
<3 RK_PB7 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
rockchip,pins =
/* gmac1_rxclkm0 */
<3 RK_PA7 3 &pcfg_pull_none>,
/* gmac1_txclkm0 */
<3 RK_PA6 3 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
rockchip,pins =
/* gmac1_rxd2m0 */
<3 RK_PA4 3 &pcfg_pull_none>,
/* gmac1_rxd3m0 */
<3 RK_PA5 3 &pcfg_pull_none>,
/* gmac1_txd2m0 */
<3 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
/* gmac1_txd3m0 */
<3 RK_PA3 3 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
gmac1m1_miim: gmac1m1-miim {
rockchip,pins =
/* gmac1_mdcm1 */
<4 RK_PB6 3 &pcfg_pull_none>,
/* gmac1_mdiom1 */
<4 RK_PB7 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m1_clkinout: gmac1m1-clkinout {
rockchip,pins =
/* gmac1_mclkinoutm1 */
<4 RK_PC1 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m1_rx_er: gmac1m1-rx-er {
rockchip,pins =
/* gmac1_rxerm1 */
<4 RK_PB2 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m1_rx_bus2: gmac1m1-rx-bus2 {
rockchip,pins =
/* gmac1_rxd0m1 */
<4 RK_PA7 3 &pcfg_pull_none>,
/* gmac1_rxd1m1 */
<4 RK_PB0 3 &pcfg_pull_none>,
/* gmac1_rxdvcrsm1 */
<4 RK_PB1 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m1_tx_bus2: gmac1m1-tx-bus2 {
rockchip,pins =
/* gmac1_txd0m1 */
<4 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
/* gmac1_txd1m1 */
<4 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
/* gmac1_txenm1 */
<4 RK_PA6 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac1m1_rgmii_clk: gmac1m1-rgmii-clk {
rockchip,pins =
/* gmac1_rxclkm1 */
<4 RK_PA3 3 &pcfg_pull_none>,
/* gmac1_txclkm1 */
<4 RK_PA0 3 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
gmac1m1_rgmii_bus: gmac1m1-rgmii-bus {
rockchip,pins =
/* gmac1_rxd2m1 */
<4 RK_PA1 3 &pcfg_pull_none>,
/* gmac1_rxd3m1 */
<4 RK_PA2 3 &pcfg_pull_none>,
/* gmac1_txd2m1 */
<3 RK_PD6 3 &pcfg_pull_none_drv_level_2>,
/* gmac1_txd3m1 */
<3 RK_PD7 3 &pcfg_pull_none_drv_level_2>;
};
};The last gmac1m1_rgmii_bus contains 3 RK_PD6 and 3 RK_PD7 4 RK_PA1 4 RK_PA2. These 3 IOs are all within the scope of the schematic diagram. The corresponding IOs can be found in gmac1m1_xxx. Then fill in the corresponding gmac1m1_xxx in DTS
tx_delay rx_delay test can refer to Rockchip_Developer_Guide_Linux_GMAC_RGMII_Delayline_CN.pdf
Find phy_lb_scan and execute echo 1000 > phy_lb_scan to get the corresponding value.
All the above are smooth, and the Ethernet can work. Here are a few special cases:
1 After the configuration is completed, the Ethernet cannot be used after booting. The measurement hardware found that the reset IO is always high. Checking the log found that the reset IO has been used by other places, and it is normal after removing it.
2 rgmii-rxid mode
When the hardware enables the RX delay of the PHY, such as RTL8211F
It is necessary to turn off the RX delay of the master, and the dts configuration mode becomes "rgmii-rxid", for example
&gmac0 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";
clock_in_out = "output";
......
tx_delay = <0x43>;
/* rx_delay = <0x42>; */
phy-handle = <&rgmii_phy>;
status = "okay";
}