1. The trace length should include the length of vias and package pads.
2. The wiring angle is preferably 135°, and the wiring at any angle will cause process problems in plate making.
Figure 1 Angle of PCB routing
3. Avoid right-angle or acute-angle wiring for wiring, which will cause changes in line width and impedance at corner positions, resulting in signal reflection, as shown in Figure 2.
Figure 2 Acute angle and right angle routing of traces
4. The wiring should go out from the long direction of the pad, and avoid going out from the wide direction or the four corners of the pad. The corner of the wiring should be more than 6mil away from the pad position, as shown in Figure 3
Figure 3 PCB leads out along the long side of the pad
5. As shown in Figure 4, the adjacent pads are connected to the same network and cannot be directly connected. It is necessary to connect the pads first before connecting. Direct connection is easy to connect tin during manual soldering.
Figure 4 The connection method of the same network pad routing
6. For small CHIP devices, pay attention to the symmetry of the wiring and keep the wiring width of the two ends consistent. For example, one pin is copper-plated, and the other pin is also copper-plated as much as possible to reduce device drift and rotation after component placement, as shown in the figure 5.
Figure 5 Correct lead-out of CHIP pads
7. For signals that require ground covering, the integrity of the ground covering must be ensured. Try to ensure that GND holes are drilled on the ground covering wires. The distance between the two GND holes should not be too far, and try to keep it at about 50-150mil, as shown in the figure 6.
Figure 6 PCB ground routing
8. The wiring should have a complete and continuous reference layer plane to avoid high-speed signal cross-area. It is recommended that the high-speed signal be at least 40mil away from the edge of the reference plane, as shown in Figure 7.
Figure 7 Segmentation of traces
9. Since the pad of the surface mount device will lead to a decrease in impedance, in order to reduce the impact of the sudden change in impedance, it is recommended to dig out a layer of reference layer directly under the pad of the surface mount according to the size of the pad. Commonly used surface mount devices include: capacitors, ESD, common mode suppression inductors, connectors, etc., as shown in Figure 8.
10. As shown in Figure 9, the area of the loop formed by the signal line and its loop should be as small as possible. The loop area is small, the external radiation is small, and the interference from the outside world is also small.
Figure 8 Hollowing treatment of labeling device pads
Figure 9 Reduction of the loop area of wiring
11. As shown in Figure 10, stubs are not allowed in the wiring, and the stub length should be minimized in the wiring. It is recommended that the stub length be zero. And to avoid the via stub effect, especially when the stub length exceeds 12mil, it is recommended to evaluate the impact of the via stub on signal integrity through simulation, as shown in Figure 11.
Figure 10 Stub routing and routing stubs
Figure 11 The stump of the via hole
12. Try to avoid traces forming self-loops on different layers. This kind of problem is easy to appear in the multilayer board design, and the self-loop will cause radiation interference. As shown in Figure 12.
Figure 12 Self-loop of PCB layout
13. It is recommended not to place test points on high-speed signals.
14. For signals that will cause interference or are sensitive (such as radio frequency signals), a shielding cover must be planned. The width of the shielding cover is usually 40mil (generally keep more than 30mil, you can confirm with the customer manufacturer), and as many GND via holes as possible on the shielding cover , to increase its welding effect. As shown in Figure 13.
Figure 13 Shield treatment of sensitive modules
15. The wiring width of the same network should be consistent. The change of the line width will cause the uneven characteristic impedance of the line, and reflection will occur when the transmission speed is high. Under certain conditions, such as connector lead-out wires and BGA package lead-out wires, the change in line width may not be avoided due to the small spacing, and the effective length of the inconsistent part in the middle should be minimized, as shown in Figure 14.
Figure 14 Sudden changes in line width
16. The line width of the IC pin outgoing line should be less than or equal to the pad width, and the outgoing line width cannot be larger than the pad width. Some signals have a wider line width due to current-carrying requirements, and the wiring can be kept consistent with the pin width first. After the wiring leads out to the pad, the line width is thickened at about 6-10mil, as shown in Figure 15.
Figure 15 The trace should not exceed the width of the pad
17. The wiring must be connected to the center of the pad and via.
18. If there is a high-voltage signal, the creepage distance must be guaranteed, and the specific parameters are shown in 16.
Figure 16 Creepage distance and clearance table
19. If the design includes multiple DDR or other memory chips, you must confirm the wiring topology with the customer and confirm whether there are reference documents.
20. The gold finger area needs to be treated with a whole window. When designing a multi-layer board, the copper of all layers below the gold finger should be hollowed out. The distance between the hollowed out copper skin and the board frame is generally more than 3mm, as shown in Figure 17.
Figure 17 Window opening and hollowing out of gold finger
21. For wiring, the channel situation at the bottleneck position should be planned in advance, and the wiring capacity at the narrowest part of the channel should be reasonably planned.
Figure 18 PCB routing channel
22. Place the coupling capacitor as close to the connector as possible.
23. The series resistance should be placed close to the sending end device, and the termination resistance should be placed close to the end. For example, the series resistance on the eMMC clock signal is recommended to be placed close to the CPU side (within 400mil).
24. It is recommended to drill a ground via hole on the ground pad of IC (such as eMMC particles, FLASH particles, etc.) to effectively shorten the reflow path, as shown in Figure 19.
Figure 19 Via drilling of the GND pad
25. It is recommended that each ground pad of the ESD device have a ground via hole, and the via hole should be as close to the pad as possible, as shown in Figure 20.
Figure 20 Drilling holes for the GND pad of the ESD device
26. Avoid wiring around clock devices (such as crystals, crystal oscillators, clock generators, clock distributors), switching power supplies, magnetic devices, and plug-in vias.
27. When the wiring layer is changed, and the reference layer before and after the layer change is the ground plane, it is necessary to place an accompanying via next to the signal via to ensure the continuity of the return path. For differential signals, signal vias and return vias should be placed symmetrically, as shown in Figure 21(a); for single-ended signals, it is recommended to place a return via next to the signal via to reduce crosstalk between vias. As shown in Figure 21(b).
Figure 21(a) Schematic diagram of differential layer-changing vias
Figure 21(b) Schematic diagram of layer-changing vias for single-ended signals
28. The distance between the ground copper skin of the connector and the signal PAD must be at least 3 times the line width, as shown in Figure 22.
Figure 22 Space requirements between GND copper skin and connector PAD
29. Use traces to connect the disconnected parts of the plane in the BGA area, or perform disk cutting to avoid destroying the integrity of the plane, as shown in Figure 23.
Figure 23 Treatment of the plane copper skin in the BGA area
30. When the PCB wiring needs to be covered with ground, the recommended way is as follows, as shown in Figure 24, L is the distance between the ground wire and the signal line; D is the distance between the ground wire and the signal line, it is recommended to be ≥4*W .
31. Some important high-speed single-ended signals, such as clock signals, reset signals, etc. (such as emmc_clk, emmc_datastrobe, RGMII_CLK, etc.) are recommended to be grounded. At least one ground hole must be drilled every 500mil for the ground wire, as shown in Figure 25.
Figure 24 PCB ground package wiring
Figure 25 Ground wrapping treatment of important signal lines
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