Turn: https://blog.csdn.net/zhong_ethan/article/details/106722753
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This article mainly introduces the rules in the cdc_setup process—clock_info1, reset_info1, setup_clock01, which report the clock tree and reset tree in the design.
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Clock_info01
Reports the clock signals in the design. spyglass can recognize the following types of clock
describe | clock type |
---|---|
common input clock | Primary Clocks |
Clock output by blackbox or process library unit | Black box clocks |
Clock output from registers or process library cells | Derived Clocks |
Floating wire-OR gated latch (gate not open) outputs the clock | Undrived Clocks |
In addition to the above cases, the clock output of the latch, tri-state device or combinational logic | Gated Clocks |
module top (d,q,clk1,sr):
input [3: 0]d;
input clk1, sr;
output [3: 0]q;
reg [3: 0]q:
reg clk3;
wire clk2, clk4, w1;
BB(clk1, clk2, w1);
always @(posedge clk1)
q[0]=d[0];
always @(negedge clk2
q[1]=d[1];
always @(posedge clk3)
q[2]=d[2];
always @(posedge clk1)
if(sr==1)
clk3=0:
else
clk3=-clk3;
always @(posedge clk4)
q[3]=d[3];
endmodule
clk1 is Primary clock, clk2 is Black box clock, clk3 is Derived Clock, clk4 is Undriven Clocks
Reset_info1
Reports synchronous reset, asynchronous reset and clear signals in the design
describe | reset type |
---|---|
normal reset | Primary Presets/Clears |
Resets generated by blackbox or process library cells | Black box Presets/Clears |
Register Generated Reset | Derived Presets/Clears |
A floating line generates a reset | Undrived Presets/Clears |
latch, a tri-state device that generates a reset | Gated Presets/Clears |
Setup_clock01
Report clock source, clock enable signal and clock cone (don't know what to translate into).
In the design, after multiple input clocks pass through the selector, only one clock is output, and the output clock is called a clock cone.