Vivado Development Tips

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Vivado is a Xilinx series FPGA development environment. This article records and collects common development skills of vivado, which are randomly recorded and updated at any time. . .

For any Xilinx-related questions, please go to WELCOME TO XILINX SUPPORT!

1. STA

Static Timing Analysis (STA): Introduction and content navigation
VIVADO's comprehensive attribute ASYNC_REG

1.1. Synchronizer

The following constraints are made in XDC, indicating that _cdc_toSTA is not performed on registers whose names end with

set_false_path -through [get_pins -hier *cdc_to*]

At the same time, for the synchronization registers that cross the clock domain, the following statement should be made. In this way, these synchronous registers can receive asynchronous signals and will be placed in the same SLICE/CLB to improve Mean Time Between Failure (MTBF)

(*ASYNC_REG = "TRUE"*)reg res_cdc_to;
(*ASYNC_REG = "TRUE"*)reg res_d1;

1.2. Report Timing Summary

For a detailed report, click Report Timing Summary under Open Implemented Design, and then select a specific path in the TIming column on the right to display the delay

In the above figure, we regard the From flip-flop as UFF0 and the To flip-flop as UFF1, then the timing path can be simplified as shown below

Nouns are explained as follows

● Slack: setup time margin
● Levels: logic levels, the number of combinational logic devices from UFF0/Q to UFF1/D
● Fanout: indicates that several destination endpoints are connected from this point, fanout = 1 means connection 1 destination endpoint
● From To: Initiate trigger and capture trigger
● Total Delay: The total delay of the path UFF0/CK to UFF1/D, that is, $T_{CK2Q}^{UFF}+T_{UFF0/Q\_to\_UFF1/D}$
● Logic Delay: the logic element delay of the path UFF0/CK to UFF1/D, including trigger delay $T_{CK2Q}^{UFF}$
● Net Delay: the routing delay from UFF0/CK to UFF1/D

It can be seen that Total Delay = Logic Delay + Net Delay

Then double-click the line of Path 5 to get the timing report of the timing path, as follows

Summary column:
● slack: setup time slack, positive means that this path meets the setup time requirement
● source: source trigger, which is the starting point of sequence analysis, launch edge (Launch Edge)
● destination: destination trigger, That is, the end point of sequence analysis, Latch Edge
● path group: clock source of timing analysis
● path type: path type, this path is the analysis of setup time
● requirement: timing requirement, set to 25MHz, so it is 40ns
● data path delay: the total delay of the path from UFF0/CK to UFF1/D, that is, $T_{CK2Q}^{UFF}+T_{UFF0/Q\_to\_UFF1/D}$
● logic levels: the number of logic levels, the number of combinational logic devices from UFF0/Q to UFF1/D
● clock path skew: the time difference between the clock arriving at the destination register and the source register
● clock uncertainty: the uncertainty of the clock degrees, including skew and jitter

Source Clock Path column:
● Delay Type: The item that generates time delay from CLK to UFF0/CK. It can be seen from the table that it is IO-route-IBUF-route-BUFG-route
● Incr(ns): the delay of each item. For example, the IBUF delay is 1.749ns, and the BUFG laboratory is 0.120ns
● Path (ns): Up to the current project, the cumulative sum of the delay. For example, the cumulative delay of IO-route-IBUF-route-BUFG is 3.709ns

Data Path column:

● Delay Type: The item that generates delay from UFF0/CK to UFF1/D. It can be seen from the table that it is the FDRE-route
● Arrival Time: the sum of the delays from the path CK to UFF1/D

and the figure below

Destination Clock Path column:

● Delay Type: Items that generate delay from path CLK to UFF1/CK, taking into account clock cycle, clock uncertainty and setup time ● Required
Time: $T_{clk}+T_{CLK2UFF1/CK}+T_{clk\_permissimon}-T_{clk\_uncertain}-T_{setup}^{UFF1}$

And satisfy Slack = Required Time - Arrival Time

"Xilinx-based Timing Analysis, Constraints and Convergence" directory and portal

2. Compile

2.1. Incremental compilation

Incremental compilation and detailed usage in vivado

2.2. Always stuck in the route_design problem

The synthesis can generate the netlist through the description, but the layout and routing have been unsuccessful, and there may be no place to put it.

You can view 工程名.runs/synth_1/runme.logthe information. The display in the text number of nodes with overlaps has been refreshing, and the value on the right side of the equal sign has not been zero. Only zero means that a feasible solution has been found for layout and routing. And each iteration iterationof WNS has been negative, resulting in stuck in the route design.

Possible reasons are as follows:

1. The IP core setting is unreasonable. For example, if the multiplier uses LUTs, it will lead to long wiring time. It should be Mults.
2. Multiple IP cores with the same name are set, it is recommended to create a new project and reset the IP
3. Is the use of clock buffers such as BUFR changed to BUFG correct?

The location of the problem can be locked by retroactively changing the content.

Router is stuck at “Number of Nodes with overlaps…”
What is “Number of Nodes with overlaps” parameter in implementation?

3. Synthesis

"Vivado Design Suite User Guide Synthesis - UG901"
Vivado tips (24): Setting synthesis properties in HDL/XDC

3.1. Report

After clicking Open Implemented Design, you can directly enter the following commands in TCL to get some reports

vivado report

utilization reportreport_utilization

Power consumption reportreport_power

congestionreport_design_analysis -congestion

Timing Violation Pathreport_design_analysis -max_paths 50 -setup

After the project is compiled, click Open Implemented Design, and then enter the following content in tcl to display the worst 50 paths

report_design_analysis -max_paths 50 -setup

3.2. IOB

In order to ensure the timing of the FPGA input and output interfaces, it is generally required to tap the input pin first before using it, and the output interface should also be tapped before outputting to the FPGA. The purpose of this is to constrain the beating registers to the IO Buffer (IOB), so that the timing of each compilation input or output will not change.

This is because the IOB is the closest register to the IO on the FPGA, and its location is fixed. When you use IOB constraints for input or output, then you can ensure that the routing delay from IBUF to register or from register to OBUF is the shortest , that is, the input routing is IO-IBUF-ILOGIC-...and the output routing is...-OLOGIC-OBUF-IO

Ensure that the timing meets the requirements to the greatest extent, and because the position of the IO is fixed, each compilation will not cause changes in the timing of the input or output.

Which signals need to be placed in the IOB? For key input and output signals, signals that require timing must be arranged on the IOB, other level signals do not need to be arranged, clock signals do not need to be arranged, and LVDS non-clock signals only need to be arranged on the p terminal.

Application of IOB of FPGA basic resources

configuration

Interface signals can be constrained in XDC

set_property  IOB true [get_ports {
    
    port_name}]

Or make constraints in verilog, as shown below

(*IOB = "TRUE"*)output res_o,
...
(*IOB = "TRUE"*) reg a;

At the same time, it must be ensured in verilog: there cannot be any sequential logic, any combinational logic, and routing branches between the input signal and the output signal and its directly connected register. And the directly connected register will be put into the IOB.

examine

After the project is compiled, open Open Implemented Design, enter in the Tcl Console below and press tclapp::install ultrafastEnter

Then enter in Tcl Console xilinx::ultrafast::report_io_regand press Enter, and the IO Ports Summary form will appear

in

● Info is a signal of Unconnected, no layout is required.
● Info is a signal of No Input FF, and its ILOGIC is 0, indicating that the input signal is not connected to the IOB. ●
Info is a signal of No Output FF, and its OLOGIC is 0, indicating that the output signal is not connected. Connect to IOB
●Info signal without information, its ILOGIC is 1 or OLOGIC is 1, which means the signal has been connected to IOB. Both ILOGIC and OLOGIC should be 1 for bidirectional signals

3.3. Safe State Machine

The default statement in the state machine means that the state machine can jump to the normal state in an abnormal state, but the EDA tool will automatically ignore the default statement, which is the result of optimizing the state machine.

The safe state machine mode changes the coding method of the state machine, and can jump to the normal state even in abnormal state, so it should be configured.

How does vivado set the safe state machine mode

configuration

The recommended writing method is to add the state registers of all state machines to the security statement in verilog, and the bit width is consistent with the actual use, that is, the definition is as follows

(*fsm_safe_state = "reset_state"*) reg [2:0] cur_state;

examine

After compiling, open工程目录下/*.runs/synth_1/runme.log

If the following content is displayed, it means that the security state machine configuration is successful

Implemented safe state 'reset_state' for state register 'cur_state_reg' in module '...'
encoded FSM with state register 'cur_state_reg' using encoding 'Hamming 2' in module '...'

If only the following content is displayed, but nothing is displayed Implemented safe state..., it means that the configuration failed

encoded FSM with state register 'cur_state_reg' using encoding 'one-hot' in module '...'

3.4. DONT_TOUCH

The DONT_TOUCH attribute can be used to protect signals or modules from being optimized out during synthesis and placement and routing. Compared with the KEEP and KEEP_HIERARCHY attributes, DONT_TOUCH can also work during layout and routing, and has a higher priority. It can be reserved for equivalent registers and equivalent combinational logic.

The sample code is as follows:

(*DONT_TOUCH = "TRUE"*) wire sig1;
assign sig1 = in1 & in2;
assign out1 = sig1 & in2;

VIVADO study notes - DONT_TOUCH
Vivado prevents signals from being synthesized in three ways
Vivado synthesis attribute series seven DONT TOUCH

3.5. MAX_FANOUT

After passing the Open Implementation Design, write the following statement in tcl to display several paths with the largest fan-out

report_high_fanout_nets
report_high_fanout_nets -help

Sets the maximum fanout limit (i.e., the maximum number of driven elements) for registers and combinational logic signals. When this setting value is exceeded, an identical register or combinatorial logic is duplicated.

(* MAX_FANOUT=50 *) reg sig1;  //Verilog示例

Vivado those things - fan-out analysis and optimization

4. Device Primitive Instantiation

That is, the Vivado source language can be regarded as a parameterized IP, and the parameter instantiation IP can be directly set without re-instantiation after setting in the IP Catalog.

Several commonly used source languages ​​are introduced below.

4.1. IO Components

Input/Output Differential Buffers (IBUFDS/OBUFDS)

For FPGA designers, it is necessary to convert an externally input differential signal into a single-ended signal, or to convert a single-ended signal into a differential signal for output. Two source languages, IBUFDS and OBUFDS, are needed. Examples are as follows

IBUFDS #(
      .DIFF_TERM	("TRUE"		),     // Differential Termination
      .IBUF_LOW_PWR	("TRUE"			),    // Low power="TRUE", Highest performance="FALSE" 
      .IOSTANDARD	("LVDS"		)     // Specify the input I/O standard
   ) IBUFDS_inst (
      .O			(data_clk_tmp	),  // Buffer output
      .I			(data_clk_p		),  // Diff_p buffer input (connect directly to top-level port)
      .IB			(data_clk_n		) 	// Diff_n buffer input (connect directly to top-level port)
   );

OBUFDS #(
      .IOSTANDARD	("LVDS"	), // Specify the output I/O standard
      .SLEW			("SLOW"		)           // Specify the output slew rate
   ) OBUFDS_inst (
      .O		(tx_frame_p	),     // Diff_p output (connect directly to top-level port)
      .OB		(tx_frame_n	),   // Diff_n output (connect directly to top-level port)
      .I		(tx_frame	)      // Buffer input 
   );

Output Double Data Rate(ODDR)

4.2. Clock Buffers

The use of Xilinx FPGA input and output buffer BUF

4.3. Xilinx Parameterized Macros(XPM)

XILINX-VIVADO IP Parameterization Method (XPM)
"Vivado Design Suite 7 SeriesFPGA and Zynq-7000 SoCLibraries Guide" - ug953

You can parameterize and instantiate IP, such as FIFO, Dual port RAM, etc., which can be found from Language Templates in vivado.

The RTL design file path of XPM IP itself is inxxx\Xilinx\Vivado\2019.1\data\ip\xpm

4.4. Unimacros

《Vivado Design Suite 7 Series FPGA and Zynq-7000 SoCLibraries Guide》 - ug9

It is also a method of parameterizing and instantiating IP, see the documentation for details

5. Project directory organization

You can directly refer to RTL Project Directory to understand how a project folder directory is organized.