Table of contents
Static timing analysis (Static Timing Analysis, STA) is one of the technologies used to verify the timing of digital design, and it is also a necessary design skill for digital IC designers.
This column blog will make reading notes on STA according to "Static Timing Analysis for Nanometer Designs: A Practical Approach", and you can also refer to the author's Zhihu column Static Timing Analysis Bible Translation Plan - Summary
This column assumes that readers have a certain basic knowledge of digital circuits.
While introducing the principle of STA, this column will also introduce design constraints and how to describe standard cells.
1 Introduction
● Timing analysis : Given a design, input clock and external environment, verify whether the design can run at the expected speed, that is, whether the design can safely run at the given clock frequency without timing violations.
The input to timing analysis is a logic design described using a hardware description language (VHDL or Verilog HDL), and timing constraints described using a constraint specification language (such as Xilinx Design Constraints, XDC or Synopsys Design Constraints, SDC). The output is the timing report.
● Static Timing Analysis (Static Timing Analysis, STA) : The timing analysis for the design is performed statically, and does not need to be stimulated on the input port.
Moreover, STA only needs to be analyzed once in the entire design, and the required timing checks can be performed on all paths in the design in all cases. Therefore, STA is a complete and exhaustive method that can be used to verify design timing.
1.1. Limitations
As follows, after reading the chapters, you will have a deep understanding of the following limitations. If you don’t understand, you can skip it directly, and finally come back to read~
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Reset sequence: Whether the flip-flop is the desired logical value after reset, which cannot be checked using STA.
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Across asynchronous clock domains: STA cannot check whether the synchronizer is used correctly, and other tools such as spyglass are needed to check
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False path (false path): The designer can specify a path that does not perform STA analysis in the design
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Clock Synchronization Logic: STA cannot detect that the clock generation logic does not match the clock definition. STA will assume that the clock generator will provide the waveform specified in the clock definition. , and STA cannot detect possible mismatches.
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Functional behavior across clock cycles: STA cannot model or simulate functional behavior that varies across clock cycles.
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Trade-off of power and speed: Designers want to use faster speed, but will be limited by power consumption.
2. STA standard unit
Various gates, flip-flops, and simple IPs in the library are called standard cells. How to describe the information of these standard cells through SDF
3. STA environment configuration
After the chip logic is designed, it is necessary to indicate various environmental information of the STA, such as clock information, chip port information, etc.
4. STA timing check
Introduce the principle and process of STA
5. Use vivado for STA
How to perform STA on the vivado platform
"Xilinx-based Timing Analysis, Constraints and Convergence" directory and portal