Preface

Do you know FPGA? I can light a lamp!

I. Overview

As a lighting expert, let’s practice it today.

How to light it?

There are 8 LED lights on the development board, and we only need to control its corresponding pin level input.

1: off; 0: on.

How to realize running water lamp?

Through the timer inside the FPGA, each LED is illuminated cyclically to achieve the effect of a running water lamp. As shown in the figure below, there are 8 LED indicators. We assign values to them in turn. Only one LED lights up at a time, and a certain LED lights up for a certain time each time (fixed delay). The 8 LEDs are lit once in sequence, and this cycle can achieve the effect of a running water lamp.

2. Code

module flow_led(
			input 			i_sys_clk,	//外部输入50MHz时钟信号
			input 			i_rst_n,	//外部输入复位信号，低电平有效
			output	[7:0] 	o_led		//8个LED指示灯接口，1--灭；0--亮
		);		

`define SIM	//仿真时使用		
		
`ifdef SIM	
	parameter MAX_CNT = 24'd10;
`else 
	parameter MAX_CNT = 24'd9_999_999;
`endif
	
//-------------------------------------
reg[23:0] cnt;		//24位计数器
reg[7:0]  led;															

	//cnt计数器进行循环计数，一个计数周期的时间为 10000000*20ns = 200ms
always @ (posedge i_sys_clk or negedge i_rst_n)									
	if(!i_rst_n) cnt <= 24'd0;											
	else if(cnt < MAX_CNT) cnt <= cnt+1'b1;	
	else cnt <= 24'd0;

//-------------------------------------

	//计数器cnt计数到最大值时，切换点亮的指示灯
always @ (posedge i_sys_clk or negedge i_rst_n) 
	if(!i_rst_n) led <= 8'b1111_1110;	//默认只点亮一个指示灯D2
	else if(cnt == MAX_CNT) led <= {led[6:0],led[7]};	//200ms为一个计数周期，执行一次循环移位操作

assign  o_led = led;		
	

endmodule

2.1 Code description

`define SIM

`ifdef SIM

parameter MAX_CNT = 24'd10;

`else

parameter MAX_CNT = 24'd9_999_999;

`endif

It means that if SIM is defined in the code, the assignment of MAX_CNT = 24'd10 will be performed; otherwise, the assignment of MAX_CNT = 24'd9_999_999 will be performed. Then we use this definition. The values of MAX_CNT are different in simulation and board level. If you want to see the results quickly during simulation, then the count value is smaller, and we can see the function implementation; in the board level case, the running water lamp The speed cannot be too fast (too fast and you will not be able to see the effect of the running water lamp), and there must be at least a few hundred milliseconds of delay before you can see the effect of the running water lamp clearly. Therefore, when doing simulation, you need to have the statement "`define SIM", and when doing actual board-level compilation, you must comment this statement.

3. Simulation

`timescale 1ns / 1ps

`timescale 1ns/1ps
module flow_led_tb();
	
reg sys_clk_i;	
reg ext_rst_n;	
wire[7:0] led;	
	
flow_led		u_flow_led(
			.i_sys_clk(sys_clk_i),	
			.i_rst_n(ext_rst_n),	
			.o_led(led)		
		);			
	
initial begin
	sys_clk_i = 0;
	ext_rst_n = 0;	//复位中
	#1000;
	@(posedge sys_clk_i); #2;
	ext_rst_n = 1;	//复位结束，正常工作
	#5000;
	$finish;
end	
	
always #10 sys_clk_i = ~sys_clk_i;	//50MHz时钟产生
	
endmodule

In order to facilitate viewing, we first select the signal led[7:0], and then right-click in the Value column, as shown in the figure below, click Radix --> Binary in the pop-up menu, which means it is displayed in binary mode.

The LED signal is displayed in binary system. We can more intuitively see that 1 bit in the 8-bit data is 0, and it keeps moving to the left, reaching the highest bit and then returning to the lowest bit.

4. Get on the board

The process of generating bit/mcs files is not long-winded. Here is a brief look at the constraint files :

set_property IOSTANDARD LVTTL [get_ports sys_clk_i]

set_property PACKAGE_PIN N11 [get_ports sys_clk_i]



set_property IOSTANDARD LVTTL [get_ports ext_rst_n]

set_property PACKAGE_PIN T2 [get_ports ext_rst_n]



set_property IOSTANDARD LVTTL [get_ports {led[0]}]

set_property PACKAGE_PIN M1 [get_ports {led[0]}]

set_property IOSTANDARD LVTTL [get_ports {led[1]}]

set_property PACKAGE_PIN N1 [get_ports {led[1]}]

set_property IOSTANDARD LVTTL [get_ports {led[2]}]

set_property PACKAGE_PIN P1 [get_ports {led[2]}]

set_property IOSTANDARD LVTTL [get_ports {led[3]}]

set_property PACKAGE_PIN R2 [get_ports {led[3]}]

set_property IOSTANDARD LVTTL [get_ports {led[4]}]

set_property PACKAGE_PIN T3 [get_ports {led[4]}]

set_property IOSTANDARD LVTTL [get_ports {led[5]}]

set_property PACKAGE_PIN R5 [get_ports {led[5]}]

set_property IOSTANDARD LVTTL [get_ports {led[6]}]

set_property PACKAGE_PIN R6 [get_ports {led[6]}]

set_property IOSTANDARD LVTTL [get_ports {led[7]}]

set_property PACKAGE_PIN T7 [get_ports {led[7]}]





set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]

Board effect:

slightly.

Later, image acquisition and Ethernet communication and other projects will be put on the board.

postscript

Other common things like adders, button debouncing, FIFP IP creation, etc. to make up for the number of words will not be written in this series. The columns are just like "FPGA Interface", focusing on practicality.

For the next project, we will start virtual project teaching, which is generally used as onboarding training for the company .

See you next time~

[FPGA Project] The first project, let’s light a lamp~