1. Calculation and simulation of LC resonant frequency
LC resonant frequency calculation formula: 
① In LoRa radio frequency circuits, LC resonant circuits are often used to filter out the second and third harmonics. The following is the LoRa radio frequency reference circuit:
LoRa second harmonics are mainly generated by the parallel connection of capacitors and inductors at the red circle position. Frequency to filter out, 9.5nH and 3.0pF parallel resonance frequency calculation: 
parallel resonance circuit and S parameter simulation diagram are as follows:
the insertion loss (<-30dB) caused by parallel resonance has a bandwidth of 15M, and the bandwidth range is relatively narrow. During the debugging process, Try to make the resonant frequency fall at the starting position of the second harmonic of the LoRa frequency band (for example, 470M~510M), which is the 940M position of the 470M second harmonic. If the resonant frequency is too far forward, the 510M second harmonic will be too high and may pass Follow-up filtering is used to suppress it; too far back will cause the 470M harmonic to be too high, and the harmonic mutation at this position is relatively large, and there is basically no effective method to suppress it.
② By connecting capacitors (C8, C9) in parallel on the left and right sides to further improve the suppression of the right side of the resonant frequency and reduce the return loss in the LoRa frequency band (470MHz), the S parameter simulation diagram is as follows: In actual debugging, increase the 
two A parallel capacitor will increase the transmit power of LoRa, but it will also worsen the second harmonic, so a compromise should be considered during the debugging process to ensure that both meet the test standards.
③The inductor (L4) and the capacitor (C7) are connected in parallel to form a low-pass filter to suppress high-order harmonics. The S-parameter simulation diagram is as follows: The S-parameter simulation diagram
applied to the radio frequency path is as follows:
④But during the actual debugging process, the above The RF circuit cannot achieve the expected debugging results, and the second harmonic may exceed the standard. This will add a level of filtering after the RF switch to suppress the second harmonic, but at the same time it will increase the return loss of the RF path and reduce the Transmit power.
The above are only simulation results under ideal conditions and are for reference only. The following picture shows the actual debugging results of LR36:
As can be seen from the above figure, the LC resonant frequency is around 940M. The frequency harmonics change greatly before 940M, so you need to pay attention to the selection of the resonant frequency during the debugging process.
2. Development summary
1. The inductor (L3) and capacitor are connected in parallel to generate a resonant frequency to suppress the second harmonic;
2. Adjust the parallel capacitor (C7, C8, C9) to fine-tune the power and harmonics. According to actual tests, the impact of C8 and C9 on the transmit power is compared. 3.
The inductor (L4) does not significantly suppress high-order harmonics, and the capacitor (C6) also participates in matching and DC blocking, but increasing or decreasing the matching effect is not obvious, so these two devices are basically incompatible. Debugging will be carried out;
4. If the resonant frequency has poor suppression of the second harmonic, you can try to add a first-level filter after the RF switch to further suppress the second harmonic;